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48f7170772
Error out if an encoding position is invalid, like an "r" operand matches an "xmmrm" operand. Document the instruction encoding symbols; there are too many of them by now. Add symbols 'n' and 'w' meaning immediates that are supposed to be encoded as if they were 'm' memory addresses and 'v' register numbers, respectively; this is necessary to indicate a validation exception. Remove broken ARPL "memory-like" encoding. It probably never worked anyway. This verification caught two bugs already: - VPMASKMOV[DQ] cannot omit the second operand. - Incorrect operand encoding order for VREDUCESH. Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
188 lines
12 KiB
Plaintext
188 lines
12 KiB
Plaintext
Bytecode specification
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----------------------
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These are the bytecodes generated by x86/insn.pl into x86/insnsb.c
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and consumed by asm/assemble.c and disasm/disasm.c.
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Values prefixed with \ are in octal, values prefixed with \x are in
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hexadecimal.
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The mnemonics are the ones used in x86/insns.dat, where applicable.
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In x86/insns.dat, the encoding slot of each operand is encoded as:
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- implicit operand (no encoding)
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x+y multiple encoding slots for one operand
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r "r" position in modr/m, or base register with "+r"
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m "m" position in modr/m
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n immediate encoded in the "m" position in modr/m
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b register encoded in the "m" position in modr/m
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x register encoded in the "x" position in modr/m + sib (MIB)
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v "v" register position in vex/evex
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s "s" registe rposition in /is4
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w immediate encoded in the "v" position in vex/evex
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i first immediate or mem_offs
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j second immediate or mem_offs
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Codes Mnemonic Explanation
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\0 terminates the code. (Unless it's a literal of course.)
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\1..\4 that many literal bytes follow in the code stream
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\5 add 4 to the primary operand number (b, low octdigit)
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\6 add 4 to the secondary operand number (a, middle octdigit)
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\7 add 4 to both the primary and the secondary operand number
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\10..\13 a literal byte follows in the code stream, to be added
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to the register value of operand 0..3
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\14..\17 the position of index register operand in MIB (BND insns)
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\20..\23 ib a byte immediate operand, from operand 0..3
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\24..\27 ib,u a zero-extended byte immediate operand, from operand 0..3
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\30..\33 iw a word immediate operand, from operand 0..3
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\34..\37 iwd select between \3[0-3] and \4[0-3]
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depending on the *operand* size of the instruction.
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\40..\43 id a long immediate operand, from operand 0..3
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\44..\47 iwdq select between \3[0-3], \4[0-3] and \5[4-7]
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depending on the *address* size of the instruction.
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\50..\53 rel8 a byte relative operand, from operand 0..3
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\54..\57 iq a qword immediate operand, from operand 0..3
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\60..\63 rel16 a word relative operand, from operand 0..3
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\64..\67 rel select between \6[0-3] and \7[0-3] depending on 16/32 bit
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assembly mode or the operand-size override on the operand
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\70..\73 rel32 a long relative operand, from operand 0..3
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\74..\77 seg a word constant, from the _segment_ part of operand 0..3
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\1ab /r a ModRM, calculated on EA in operand a, with the reg
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field the register value of operand b.
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\171\mab /mrb (e.g /3r0) a ModRM, with the reg field taken from operand a, and the m
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and b fields set to the specified values.
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\172\ab /is4 the register number from operand a in bits 7..4, with
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the 4-bit immediate from operand b in bits 3..0.
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\173\xab the register number from operand a in bits 7..4, with
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the value b in bits 3..0.
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\174..\177 the register number from operand 0..3 in bits 7..4, and
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an arbitrary value in bits 3..0 (assembled as zero.)
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\2ab /b a ModRM, calculated on EA in operand a, with the reg
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field equal to digit b.
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\240..\243 this instruction uses EVEX rather than REX or VEX/XOP, with the
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V register number taken from operand "b" (0..3) (which may
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be an immediate, as is used for DFV.)
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\250 this instruction uses EVEX rather than REX or VEX/XOP, with the
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V register number set to 0 (subject to the XOR as defined
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below)
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EVEX prefixes are followed by the sequence:
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\p1\p2\p3\3tt
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... which are XOR'd into the EVEX payload bytes. These are used to encode the
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map and other fixed fields. Note that the inverted register bits should be
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set to 1.
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These are used in conjunction with the following instruction flags:
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IF_LIG hint to the disassembler: ignore EVEX.L
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IF_WIG hint to the disassembler: ignore EVEX.W
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IF_WW W is used as REX_W
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IF_NF the {nf} prefix is permitted for this instruction
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IF_DFV this instruction uses the V field as DFV
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tt is tuple type for Disp8*N from %tuple_codes in insns.pl
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(compressed displacement encoding)
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\254..\257 id,s a signed 32-bit operand to be extended to 64 bits.
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\260..\263 this instruction uses VEX/XOP rather than REX, with the
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V register taken from operand "b" 0..3.
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\264..\267 id,u an unsigned 32-bit operand to be extended to 64 bits.
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\270 this instruction uses VEX/XOP rather than REX, with the
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V register set to 0.
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VEX/XOP prefixes are followed by the sequence:
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\tmm\wlp tmm format: tt 0mm mmm
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[vex] tt = 0
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[xop] tt = 1
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mmmmm = M field
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wlp format: w0 00l lpp
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[l0] ll = 0 for L = 0 (.128, .lz)
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[l1] ll = 1 for L = 1 (.256)
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[lig] ll = 0 for L don't care (always assembled as 0) with IF_LIG
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[w0] w = 0 for W = 0
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[w1 ] w = 1 for W = 1
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[wig] w = 0 for W don't care (always assembled as 0) with IF_WIG
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[ww] w = 0 for W used as REX.W with IF_WW
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t = 0 for VEX (C4/C5), t = 1 for XOP (8F).
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\271 hlex instruction takes XRELEASE (F3) with or without lock
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\272 hlenl instruction takes XACQUIRE/XRELEASE with or without lock
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\273 hle instruction takes XACQUIRE/XRELEASE with lock only
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\274..\277 ib,s a byte immediate operand, from operand 0..3, sign-extended
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to the operand size (if o16/o32/o64 present) or the bit size
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\300..\303 ibn a valid 0F NOP opcode.
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\304..\307
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\0\xNN ib^NN intermediate byte XOR 0xNN
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\1\xNN ib,s^NN signed intermediate byte XOR 0xNN
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\2\xNN ib,u^NN unsigned intermediate byte XOR 0xNN
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\310 a16 indicates fixed 16-bit address size, i.e. optional 0x67.
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\311 a32 indicates fixed 32-bit address size, i.e. optional 0x67.
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\312 adf, asz (disassembler only) invalid with non-default address size.
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\313 a64 indicates fixed 64-bit address size, 0x67 invalid.
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\314 norexb (disassembler only) invalid with REX.B
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\315 norexx (disassembler only) invalid with REX.X
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\316 norexr (disassembler only) invalid with REX.R
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\317 norexw (disassembler only) invalid with REX.W
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- o8 generates no byte code; for orthogonality.
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\320 o16* indicates fixed 16-bit operand size, i.e. optional 0x66.
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\321 o32* indicates fixed 32-bit operand size, i.e. optional 0x66.
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\322 odf indicates that this instruction is only valid when the
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operand size is the default (instruction to disassembler,
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generates no code in the assembler)
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\323 o64nw indicates fixed 64-bit operand size (equivalent to nw o64)
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\324 o64 indicates 64-bit operand size requiring REX.W.
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\325 nohi instruction which always uses spl/bpl/sil/dil
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\326 nof3 (disassembler only) not valid with 0xF3 REP prefix.
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\327 nw indicates that the operand size defaults to 64 in 64-bit mode;
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REX.W is not required. As a side effect, 32-bit operand size is
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not available. If followed by an oxx code, this has the
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following effects:
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o16 - 66 prefix generated in 32- or 64-bit mode.
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o32 - 66 prefix generated in 16-bit mode; treated as o64 in 64-bit mode.
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o64 - only permitted in 64-bit mode, does not set REX.W unless combined
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with code rex.w (\347).
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\330 osz default or user-specified operand size
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\331 norep not valid with 0xF2 or 0xF3 REP prefixes.
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\332 f2 REP prefix (0xF2 byte) used as opcode extension.
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\333 f3 REP prefix (0xF3 byte) used as opcode extension.
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\334 rex.l LOCK prefix used as REX.R in 16/32-bit mode.
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\335 repe disassemble a rep (0xF3 byte) prefix as repe not rep.
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\336 optw 16-, 32- and 64-bit operation identical; allow optimization.
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\337 optd 32- and 64-bit operation identical; allow optimization.
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\340 resb reserve <operand 0> bytes of uninitialized storage.
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Operand 0 had better be a segmentless constant.
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\341 wait this instruction needs a WAIT "prefix"
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\342 osm o16, o32 or o64 matching bit mode
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\343 osd o16, o32 or o32 matching bit mode
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\344 rex.b REX[2].B used as an opcode extension.
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\345 rex.x REX[2].X used as an opcode extension.
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\346 rex.r REX[2].R used as an opcode extension.
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\347 rex.w REX[2].W used as an opcode extension.
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\350..\351 rex2[.w] obligatory REX2 prefix, rex2.w = rex.w rex2
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\355..\357 m[1-3] 0f 0f38 0f3a Set the legacy map number. Unless a REX2, VEX, or EVEX prefix
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is also generated, these are emitted as legacy prefix bytes.
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- m0 Generates no byte code, but can be used to indicate that
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following bytes are literal and not part of a prefix.
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\360 np no SSE prefix (== \364\331)
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\361 66 66 SSE prefix (== \366\331)
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\364 !osp operand-size prefix (0x66) not permitted
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\365 !asp address-size prefix (0x67) not permitted
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\366 osp operand-size prefix (0x66) used as opcode extension
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\367 67 address-size prefix (0x67) used as opcode extension
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\370,\371 jcc8 match only if operand 0 meets byte jump criteria.
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jmp8 370 is used for Jcc, 371 is used for JMP.
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\373 jlen assemble 0x03 if bits==16, 0x05 if bits==32;
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used for conditional jump over longer jump
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\374 vsibx|vm32x|vm64x this instruction takes an XMM VSIB memory EA
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\375 vsiby|vm32y|vm64y this instruction takes an YMM VSIB memory EA
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\376 vsibz|vm32z|vm64z this instruction takes an ZMM VSIB memory EA
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* No 66 prefix is emitted if combined with VEX/EVEX, np, 66, osp or !osp.
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