H. Peter Anvin acd01496d7 asm: distinguish between VEX.V as an immediate and a prefix; fix WW ...

If VEX.V is an immediate, it should not be subject to register range
checks.

If the WW flag is set, REX_W needs to be OR'd in, not XOR'd, because
the map might have the W bit set for matching purposes.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>

2025-09-02 15:38:49 -07:00

..

bytecode.txt

assemble: rex2.w; hinted Jcc in 64-bit mode; UDB

2025-08-29 13:55:30 -07:00

iflags.ph

asm: distinguish between VEX.V as an immediate and a prefix; fix WW

2025-09-02 15:38:49 -07:00

insns-iflags.ph

insns: add PROT flag if either EVEX or LONG is set

2024-08-23 13:15:46 -07:00

insns.dat

asm: distinguish between VEX.V as an immediate and a prefix; fix WW

2025-09-02 15:38:49 -07:00

insns.pl

asm: distinguish between VEX.V as an immediate and a prefix; fix WW

2025-09-02 15:38:49 -07:00

preinsns.pl

Add optimization for operand narrowing; tidy up selector handling

2024-08-23 02:25:21 -07:00

regs.dat

ndisasm: make the assembler (hopefully) work again

2025-08-30 16:16:43 -07:00

regs.pl

ndisasm: make the assembler (hopefully) work again

2025-08-30 16:16:43 -07:00

rex2.pl

x86: add Perl script for rex2 compatibility testing (not yet used)

2025-03-04 08:43:09 -08:00

x86const.h

apx: modify the tokenizer to be able to handle {dfv=...}

2024-07-27 17:57:08 -07:00