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cc1dc9de53
EVEX encoding support includes 32 vector regs (XMM/YMM/ZMM), opmask, broadcasting, embedded rounding mode, suppress all exceptions, compressed displacement. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
254 lines
15 KiB
C
254 lines
15 KiB
C
/* ----------------------------------------------------------------------- *
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*
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* Copyright 1996-2012 The NASM Authors - All Rights Reserved
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* See the file AUTHORS included with the NASM distribution for
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* the specific copyright holders.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following
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* conditions are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
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* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* ----------------------------------------------------------------------- */
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/*
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* opflags.h - operand flags
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*/
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#ifndef NASM_OPFLAGS_H
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#define NASM_OPFLAGS_H
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#include "compiler.h"
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#include "tables.h" /* for opflags_t and nasm_reg_flags[] */
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/*
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* Here we define the operand types. These are implemented as bit
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* masks, since some are subsets of others; e.g. AX in a MOV
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* instruction is a special operand type, whereas AX in other
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* contexts is just another 16-bit register. (Also, consider CL in
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* shift instructions, DX in OUT, etc.)
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*
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* The basic concept here is that
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* (class & ~operand) == 0
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*
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* if and only if "operand" belongs to class type "class".
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*/
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#define OP_GENMASK(bits, shift) (((UINT64_C(1) << (bits)) - 1) << (shift))
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#define OP_GENBIT(bit, shift) (UINT64_C(1) << ((shift) + (bit)))
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/*
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* Type of operand: memory reference, register, etc.
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*
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* Bits: 0 - 3
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*/
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#define OPTYPE_SHIFT (0)
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#define OPTYPE_BITS (4)
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#define OPTYPE_MASK OP_GENMASK(OPTYPE_BITS, OPTYPE_SHIFT)
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#define GEN_OPTYPE(bit) OP_GENBIT(bit, OPTYPE_SHIFT)
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/*
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* Modifiers.
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*
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* Bits: 4 - 6
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*/
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#define MODIFIER_SHIFT (4)
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#define MODIFIER_BITS (3)
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#define MODIFIER_MASK OP_GENMASK(MODIFIER_BITS, MODIFIER_SHIFT)
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#define GEN_MODIFIER(bit) OP_GENBIT(bit, MODIFIER_SHIFT)
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/*
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* Register classes.
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*
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* Bits: 7 - 16
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*/
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#define REG_CLASS_SHIFT (7)
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#define REG_CLASS_BITS (10)
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#define REG_CLASS_MASK OP_GENMASK(REG_CLASS_BITS, REG_CLASS_SHIFT)
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#define GEN_REG_CLASS(bit) OP_GENBIT(bit, REG_CLASS_SHIFT)
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/*
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* Subclasses. Depends on type of operand.
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*
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* Bits: 17 - 24
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*/
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#define SUBCLASS_SHIFT (17)
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#define SUBCLASS_BITS (8)
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#define SUBCLASS_MASK OP_GENMASK(SUBCLASS_BITS, SUBCLASS_SHIFT)
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#define GEN_SUBCLASS(bit) OP_GENBIT(bit, SUBCLASS_SHIFT)
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/*
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* Special flags. Context dependant.
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*
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* Bits: 25 - 31
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*/
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#define SPECIAL_SHIFT (25)
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#define SPECIAL_BITS (7)
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#define SPECIAL_MASK OP_GENMASK(SPECIAL_BITS, SPECIAL_SHIFT)
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#define GEN_SPECIAL(bit) OP_GENBIT(bit, SPECIAL_SHIFT)
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/*
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* Sizes of the operands and attributes.
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*
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* Bits: 32 - 42
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*/
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#define SIZE_SHIFT (32)
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#define SIZE_BITS (11)
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#define SIZE_MASK OP_GENMASK(SIZE_BITS, SIZE_SHIFT)
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#define GEN_SIZE(bit) OP_GENBIT(bit, SIZE_SHIFT)
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/*
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* Bits distribution (counted from 0)
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*
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* 6 5 4 3 2 1
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* 3210987654321098765432109876543210987654321098765432109876543210
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* |
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* | dword bound
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*
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* ............................................................1111 optypes
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* .........................................................111.... modifiers
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* ...............................................1111111111....... register classes
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* .......................................11111111................. subclasses
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* ................................1111111......................... specials
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* .....................11111111111................................ sizes
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*/
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#define REGISTER GEN_OPTYPE(0) /* register number in 'basereg' */
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#define IMMEDIATE GEN_OPTYPE(1)
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#define REGMEM GEN_OPTYPE(2) /* for r/m, ie EA, operands */
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#define MEMORY (GEN_OPTYPE(3) | REGMEM)
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#define BITS8 GEN_SIZE(0) /* 8 bits (BYTE) */
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#define BITS16 GEN_SIZE(1) /* 16 bits (WORD) */
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#define BITS32 GEN_SIZE(2) /* 32 bits (DWORD) */
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#define BITS64 GEN_SIZE(3) /* 64 bits (QWORD), x64 and FPU only */
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#define BITS80 GEN_SIZE(4) /* 80 bits (TWORD), FPU only */
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#define BITS128 GEN_SIZE(5) /* 128 bits (OWORD) */
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#define BITS256 GEN_SIZE(6) /* 256 bits (YWORD) */
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#define BITS512 GEN_SIZE(7) /* 512 bits (ZWORD) */
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#define FAR GEN_SIZE(8) /* grotty: this means 16:16 or 16:32, like in CALL/JMP */
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#define NEAR GEN_SIZE(9)
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#define SHORT GEN_SIZE(10) /* and this means what it says :) */
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#define TO GEN_MODIFIER(0) /* reverse effect in FADD, FSUB &c */
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#define COLON GEN_MODIFIER(1) /* operand is followed by a colon */
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#define STRICT GEN_MODIFIER(2) /* do not optimize this operand */
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#define REG_CLASS_CDT GEN_REG_CLASS(0)
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#define REG_CLASS_GPR GEN_REG_CLASS(1)
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#define REG_CLASS_SREG GEN_REG_CLASS(2)
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#define REG_CLASS_FPUREG GEN_REG_CLASS(3)
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#define REG_CLASS_RM_MMX GEN_REG_CLASS(4)
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#define REG_CLASS_RM_XMM GEN_REG_CLASS(5)
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#define REG_CLASS_RM_YMM GEN_REG_CLASS(6)
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#define REG_CLASS_RM_ZMM GEN_REG_CLASS(7)
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#define REG_CLASS_OPMASK GEN_REG_CLASS(8)
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#define is_class(class, op) (!((opflags_t)(class) & ~(opflags_t)(op)))
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#define is_reg_class(class, reg) is_class((class), nasm_reg_flags[(reg)])
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#define IS_SREG(reg) is_reg_class(REG_SREG, (reg))
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#define IS_FSGS(reg) is_reg_class(REG_FSGS, (reg))
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/* Register classes */
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#define REG_EA ( REGMEM | REGISTER) /* 'normal' reg, qualifies as EA */
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#define RM_GPR ( REG_CLASS_GPR | REGMEM) /* integer operand */
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#define REG_GPR ( REG_CLASS_GPR | REGMEM | REGISTER) /* integer register */
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#define REG8 ( REG_CLASS_GPR | BITS8 | REGMEM | REGISTER) /* 8-bit GPR */
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#define REG16 ( REG_CLASS_GPR | BITS16 | REGMEM | REGISTER) /* 16-bit GPR */
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#define REG32 ( REG_CLASS_GPR | BITS32 | REGMEM | REGISTER) /* 32-bit GPR */
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#define REG64 ( REG_CLASS_GPR | BITS64 | REGMEM | REGISTER) /* 64-bit GPR */
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#define FPUREG ( REG_CLASS_FPUREG | REGISTER) /* floating point stack registers */
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#define FPU0 (GEN_SUBCLASS(1) | REG_CLASS_FPUREG | REGISTER) /* FPU stack register zero */
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#define RM_MMX ( REG_CLASS_RM_MMX | REGMEM) /* MMX operand */
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#define MMXREG ( REG_CLASS_RM_MMX | REGMEM | REGISTER) /* MMX register */
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#define RM_XMM ( REG_CLASS_RM_XMM | REGMEM) /* XMM (SSE) operand */
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#define XMMREG ( REG_CLASS_RM_XMM | REGMEM | REGISTER) /* XMM (SSE) register */
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#define XMM0 (GEN_SUBCLASS(1) | REG_CLASS_RM_XMM | REGMEM | REGISTER) /* XMM register zero */
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#define RM_YMM ( REG_CLASS_RM_YMM | REGMEM) /* YMM (AVX) operand */
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#define YMMREG ( REG_CLASS_RM_YMM | REGMEM | REGISTER) /* YMM (AVX) register */
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#define YMM0 (GEN_SUBCLASS(1) | REG_CLASS_RM_YMM | REGMEM | REGISTER) /* YMM register zero */
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#define RM_ZMM ( REG_CLASS_RM_ZMM | REGMEM) /* ZMM (AVX512) operand */
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#define ZMMREG ( REG_CLASS_RM_ZMM | REGMEM | REGISTER) /* ZMM (AVX512) register */
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#define ZMM0 (GEN_SUBCLASS(1) | REG_CLASS_RM_ZMM | REGMEM | REGISTER) /* ZMM register zero */
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#define RM_OPMASK ( REG_CLASS_OPMASK | REGMEM) /* Opmask operand */
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#define OPMASKREG ( REG_CLASS_OPMASK | REGMEM | REGISTER) /* Opmask register */
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#define OPMASK0 (GEN_SUBCLASS(1) | REG_CLASS_OPMASK | REGMEM | REGISTER) /* Opmask register zero (k0) */
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#define REG_CDT ( REG_CLASS_CDT | BITS32 | REGISTER) /* CRn, DRn and TRn */
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#define REG_CREG (GEN_SUBCLASS(1) | REG_CLASS_CDT | BITS32 | REGISTER) /* CRn */
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#define REG_DREG (GEN_SUBCLASS(2) | REG_CLASS_CDT | BITS32 | REGISTER) /* DRn */
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#define REG_TREG (GEN_SUBCLASS(3) | REG_CLASS_CDT | BITS32 | REGISTER) /* TRn */
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#define REG_SREG ( REG_CLASS_SREG | BITS16 | REGISTER) /* any segment register */
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/* Segment registers */
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#define REG_ES (GEN_SUBCLASS(0) | GEN_SUBCLASS(2) | REG_CLASS_SREG | BITS16 | REGISTER) /* ES */
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#define REG_CS (GEN_SUBCLASS(1) | GEN_SUBCLASS(2) | REG_CLASS_SREG | BITS16 | REGISTER) /* CS */
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#define REG_SS (GEN_SUBCLASS(0) | GEN_SUBCLASS(3) | REG_CLASS_SREG | BITS16 | REGISTER) /* SS */
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#define REG_DS (GEN_SUBCLASS(1) | GEN_SUBCLASS(3) | REG_CLASS_SREG | BITS16 | REGISTER) /* DS */
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#define REG_FS (GEN_SUBCLASS(0) | GEN_SUBCLASS(4) | REG_CLASS_SREG | BITS16 | REGISTER) /* FS */
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#define REG_GS (GEN_SUBCLASS(1) | GEN_SUBCLASS(4) | REG_CLASS_SREG | BITS16 | REGISTER) /* GS */
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#define REG_FSGS ( GEN_SUBCLASS(4) | REG_CLASS_SREG | BITS16 | REGISTER) /* FS or GS */
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#define REG_SEG67 ( GEN_SUBCLASS(5) | REG_CLASS_SREG | BITS16 | REGISTER) /* Unimplemented segment registers */
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/* Special GPRs */
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#define REG_SMASK SUBCLASS_MASK /* a mask for the following */
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#define REG_ACCUM (GEN_SUBCLASS(1) | REG_CLASS_GPR | REGMEM | REGISTER) /* accumulator: AL, AX, EAX, RAX */
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#define REG_AL (GEN_SUBCLASS(1) | REG_CLASS_GPR | BITS8 | REGMEM | REGISTER)
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#define REG_AX (GEN_SUBCLASS(1) | REG_CLASS_GPR | BITS16 | REGMEM | REGISTER)
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#define REG_EAX (GEN_SUBCLASS(1) | REG_CLASS_GPR | BITS32 | REGMEM | REGISTER)
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#define REG_RAX (GEN_SUBCLASS(1) | REG_CLASS_GPR | BITS64 | REGMEM | REGISTER)
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#define REG_COUNT (GEN_SUBCLASS(5) | GEN_SUBCLASS(2) | REG_CLASS_GPR | REGMEM | REGISTER) /* counter: CL, CX, ECX, RCX */
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#define REG_CL (GEN_SUBCLASS(5) | GEN_SUBCLASS(2) | REG_CLASS_GPR | BITS8 | REGMEM | REGISTER)
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#define REG_CX (GEN_SUBCLASS(5) | GEN_SUBCLASS(2) | REG_CLASS_GPR | BITS16 | REGMEM | REGISTER)
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#define REG_ECX (GEN_SUBCLASS(5) | GEN_SUBCLASS(2) | REG_CLASS_GPR | BITS32 | REGMEM | REGISTER)
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#define REG_RCX (GEN_SUBCLASS(5) | GEN_SUBCLASS(2) | REG_CLASS_GPR | BITS64 | REGMEM | REGISTER)
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#define REG_DL (GEN_SUBCLASS(5) | GEN_SUBCLASS(3) | REG_CLASS_GPR | BITS8 | REGMEM | REGISTER) /* data: DL, DX, EDX, RDX */
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#define REG_DX (GEN_SUBCLASS(5) | GEN_SUBCLASS(3) | REG_CLASS_GPR | BITS16 | REGMEM | REGISTER)
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#define REG_EDX (GEN_SUBCLASS(5) | GEN_SUBCLASS(3) | REG_CLASS_GPR | BITS32 | REGMEM | REGISTER)
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#define REG_RDX (GEN_SUBCLASS(5) | GEN_SUBCLASS(3) | REG_CLASS_GPR | BITS64 | REGMEM | REGISTER)
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#define REG_HIGH (GEN_SUBCLASS(5) | GEN_SUBCLASS(4) | REG_CLASS_GPR | BITS8 | REGMEM | REGISTER) /* high regs: AH, CH, DH, BH */
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#define REG_NOTACC GEN_SUBCLASS(5) /* non-accumulator register */
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#define REG8NA (GEN_SUBCLASS(5) | REG_CLASS_GPR | BITS8 | REGMEM | REGISTER) /* 8-bit non-acc GPR */
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#define REG16NA (GEN_SUBCLASS(5) | REG_CLASS_GPR | BITS16 | REGMEM | REGISTER) /* 16-bit non-acc GPR */
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#define REG32NA (GEN_SUBCLASS(5) | REG_CLASS_GPR | BITS32 | REGMEM | REGISTER) /* 32-bit non-acc GPR */
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#define REG64NA (GEN_SUBCLASS(5) | REG_CLASS_GPR | BITS64 | REGMEM | REGISTER) /* 64-bit non-acc GPR */
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/* special types of EAs */
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#define MEM_OFFS (GEN_SUBCLASS(1) | MEMORY) /* simple [address] offset - absolute! */
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#define IP_REL (GEN_SUBCLASS(2) | MEMORY) /* IP-relative offset */
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#define XMEM (GEN_SUBCLASS(3) | MEMORY) /* 128-bit vector SIB */
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#define YMEM (GEN_SUBCLASS(4) | MEMORY) /* 256-bit vector SIB */
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#define ZMEM (GEN_SUBCLASS(5) | MEMORY) /* 512-bit vector SIB */
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/* memory which matches any type of r/m operand */
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#define MEMORY_ANY (MEMORY | RM_GPR | RM_MMX | RM_XMM | RM_YMM | RM_ZMM)
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/* special immediate values */
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#define UNITY (GEN_SUBCLASS(0) | IMMEDIATE) /* operand equals 1 */
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#define SBYTEWORD (GEN_SUBCLASS(1) | IMMEDIATE) /* operand is in the range -128..127 mod 2^16 */
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#define SBYTEDWORD (GEN_SUBCLASS(2) | IMMEDIATE) /* operand is in the range -128..127 mod 2^32 */
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#define SDWORD (GEN_SUBCLASS(3) | IMMEDIATE) /* operand is in the range -0x80000000..0x7FFFFFFF */
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#define UDWORD (GEN_SUBCLASS(4) | IMMEDIATE) /* operand is in the range 0..0xFFFFFFFF */
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#endif /* NASM_OPFLAGS_H */
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