H. Peter Anvin 3efdd3cf9a assemble: rex2.w; hinted Jcc in 64-bit mode; UDB ...

- rex2.w is used as a opcode extension (JMPABS), not rex2.x1 as an
  earlier version of the spec had.
- Segment prefixes used as Jcc hints are valid in 64-bit mode.
- Avoid duplicate warning messages for ignored/invalid prefixes.
  * emit_prefixes() is called twice during code generation.
- Add the UDB #UD opcode in 64-bit mode; SALC is 16/32-bit only.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>

2025-08-29 13:55:30 -07:00

..

bytecode.txt

assemble: rex2.w; hinted Jcc in 64-bit mode; UDB

2025-08-29 13:55:30 -07:00

iflags.ph

assemble: rex2.w; hinted Jcc in 64-bit mode; UDB

2025-08-29 13:55:30 -07:00

insns-iflags.ph

insns: add PROT flag if either EVEX or LONG is set

2024-08-23 13:15:46 -07:00

insns.dat

assemble: rex2.w; hinted Jcc in 64-bit mode; UDB

2025-08-29 13:55:30 -07:00

insns.pl

assemble: rex2.w; hinted Jcc in 64-bit mode; UDB

2025-08-29 13:55:30 -07:00

preinsns.pl

Add optimization for operand narrowing; tidy up selector handling

2024-08-23 02:25:21 -07:00

regs.dat

insns: more macro goodness

2024-08-14 20:48:18 -07:00

regs.pl

regs: clean up and somewhat automate register range flags

2024-07-23 16:04:47 -07:00

rex2.pl

x86: add Perl script for rex2 compatibility testing (not yet used)

2025-03-04 08:43:09 -08:00

x86const.h

apx: modify the tokenizer to be able to handle {dfv=...}

2024-07-27 17:57:08 -07:00