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H. Peter Anvin (Intel) 9b101e9316 insns.pl: register 0 should add RN_ZERO, not RM_ZERO 
Not all registers are valid as memory references, and thus
using RM_ZERO is incorrect. Use RN_ZERO instead, which is simply the
zero-register bit.

Fixes: https://github.com/netwide-assembler/nasm/issues/140
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-10-09 15:42:29 -07:00
..
bytecode.txt
insns.pl: sanity-check that instruction encodings match operands
2025-09-30 12:06:11 -07:00
iflags.ph
Feature flag change, remove duplicate: AVX512FC16->F16C
2025-10-09 14:29:09 -07:00
insns-iflags.ph
treewide: replace verbose copyright headers with SPDX tags
2025-10-01 11:45:31 -07:00
insns.dat
AMX-TRANSPOSE: removed, retag instructions NEVER.
2025-10-09 14:44:24 -07:00
insns.pl
insns.pl: register 0 should add RN_ZERO, not RM_ZERO
2025-10-09 15:42:29 -07:00
preinsns.pl
bug in new macro (typo?): alias is SAL (to SHL), not SAR
2025-10-08 11:49:54 -07:00
regs.dat
treewide: replace verbose copyright headers with SPDX tags
2025-10-01 11:45:31 -07:00
regs.pl
x86: tools: Remove unused perl code variables
2025-10-06 19:17:51 +02:00
rex2.pl
x86: add Perl script for rex2 compatibility testing (not yet used)
2025-03-04 08:43:09 -08:00
x86const.h
apx: modify the tokenizer to be able to handle {dfv=...}
2024-07-27 17:57:08 -07:00