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https://github.com/netwide-assembler/nasm.git
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973fe19a1b
EVEX encoding is really messy, with the 4th register bit in one of several places depending on which type of register it is. It seems to work now. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
46 lines
1001 B
NASM
46 lines
1001 B
NASM
bits 64
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blendvpd xmm2,xmm1,xmm0
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vblendvpd xmm2,xmm1,xmm0,xmm0
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vblendvpd xmm2,xmm1,xmm0
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vblendvpd ymm2,ymm1,ymm0,ymm0
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vblendvpd ymm2,ymm1,ymm0
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vcvtsi2sd xmm9,xmm10,ecx
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vcvtsi2sd xmm9,xmm10,rcx
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vcvtsi2sd xmm9,xmm10,dword [rdi]
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vcvtsi2sd xmm9,xmm10,qword [rdi]
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vpextrb [rax],xmm1,0x33
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vpextrw [rax],xmm1,0x33
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vpextrd [rax],xmm1,0x33
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vpextrq [rax],xmm1,0x33
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vpextrb rax,xmm1,0x33
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vpextrw rax,xmm1,0x33
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vpextrd rax,xmm1,0x33
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vpextrq rax,xmm1,0x33
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vpextrb eax,xmm1,0x33
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vpextrw eax,xmm1,0x33
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vpextrd eax,xmm1,0x33
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; vpextrq eax,xmm1,0x33
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pextrw rax,xmm0,0x33
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vcvtpd2ps xmm0,xmm1
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vcvtpd2ps xmm0,oword [rsi]
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vcvtpd2ps xmm0,ymm1
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vcvtpd2ps xmm0,yword [rsi]
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; vcvtpd2ps xmm0,[rsi]
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vcvtpd2dq xmm0,xmm1
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vcvtpd2dq xmm0,oword [rsi]
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vcvtpd2dq xmm0,ymm1
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vcvtpd2dq xmm0,yword [rsi]
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; vcvtpd2dq xmm0,[rsi]
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vcvttpd2dq xmm0,xmm1
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vcvttpd2dq xmm0,oword [rsi]
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vcvttpd2dq xmm0,ymm1
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vcvttpd2dq xmm0,yword [rsi]
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; vcvttpd2dq xmm0,[rsi]
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