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Commit Graph

5363 Commits

Author SHA1 Message Date
H. Peter Anvin
c5faa4a452 assemble.c: don't warn about segment prefixes in 16/32-bit mode
The warning about ignored segment prefixes were incorrectly issued in
16/32-bit mode as well.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-05 00:49:49 -07:00
H. Peter Anvin
084714737a travis: confirm that crc32 test now produces the correct output
The crc32 test now does produce the correct output one would expect
for running with optimized assembly.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-05 00:45:32 -07:00
H. Peter Anvin
a2b1c752a4 insns.dat: add non-optimizing patterns for CRC32 byte
The CRC32 byte patterns are documented to be able to take a
(pointless) REX.W to "extend" the pattern to a 64-bit
destination... but that never changes the result.

However, be excrutiatingly correct and add those patterns when not
using optimization.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-05 00:41:18 -07:00
H. Peter Anvin
08969b4d38 insns.dat: fix the crc32 instructions
The crc32 instructions are kind of odd; the operand size really only
applies to the right (source) operand.

The APX forms are also kind of messy.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-05 00:19:14 -07:00
H. Peter Anvin
5ddccd6d04 travis: update apx.bin.t
Update the apx.bin.t file, since it now produces the same output as it
does with -DSRC and -DBIN.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-04 23:58:35 -07:00
H. Peter Anvin
cb20ce6f01 apx: handle RN_L16 on EAs, automatically generate EVEX forms
Memory references should have RN_L16 set if and only if they are
compatible with instruction patterns requiring register numbers below
16.

Add a "vex+" encoding pattern for VEX-encoded instructions that should
be promoted to EVEX when AVX-encoded.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-04 23:49:10 -07:00
H. Peter Anvin
e9d357ba19 Merge remote-tracking branch 'maciej/apx.wip.travis' into apx.wip 2025-09-04 20:12:16 -07:00
H. Peter Anvin
bb253780ab changes.src: update release log
Add updates to the release documentation.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-04 20:08:15 -07:00
H. Peter Anvin
6a270222be outobj: fix crash when no labels are defined in the default segment
If there are no labels in the default segment, then NASM would crash
if anything was emitted in it, as the label would be defined on the
final pass only.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-04 20:06:06 -07:00
H. Peter Anvin
31a160759d Add %ifdirective preprocessor directive
Along with C and other languages, the current trend is to be able to
probe for features rather than relying on version numbers. This is
motivated in part by the intent of bumping the major version number to
3.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-04 19:41:12 -07:00
H. Peter Anvin
ec48f1a3f8 preproc: unbreak %cond()
The previous patch accidentally broke the %cond() function.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-04 18:23:55 -07:00
H. Peter Anvin
d5bd136ced preproc: add message-generating and %null() functions
Add the %null(), %note(), %warning(), %error(), and %fatal()
functions. They behave like the corresponding directives, then expands
to nothing.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-04 17:10:42 -07:00
H. Peter Anvin
61b525fbc1 nasmlib.h: add convenience macros for iterating over fixed arrays
Iterating over fixed arrays is a common operation; add macros to
simplify the task.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-04 17:09:57 -07:00
Maciej Wieczor-Retman
5d1deaffc3 WIP apx: KMOV instructions
Add KMOV APX variants to the database. Add relevant tests.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-04 23:35:14 +02:00
Maciej Wieczor-Retman
312b89d71f x86: Fix wrong encondig of 32 bit KMOV variants
VEX.pp should be 0 for 32 bit variant of KMOV.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-04 23:35:14 +02:00
Maciej Wieczor-Retman
3387f868fd insns: travis: apx: INV instruction
Add INVPCI, INVEPT, INVVPID APX instruction variants to the database and
relevant tests.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-04 23:29:21 +02:00
Maciej Wieczor-Retman
cb453cba39 insns: travis: apx: INC instruction
Add INC test cases and the database entry.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-04 13:33:06 +02:00
Maciej Wieczor-Retman
6b137d5212 insns: travis: apx: IMUL instruction test cases and bug fix
Add the test cases for the IMUL instruction.

Fix the 0x6B database bug that used the same bit width of the immediate
operand as the other operands. Make it 8 bit wide, just like in the
legacy instruction.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-04 13:13:12 +02:00
Yongjie2017
6f3147b4ec add avx 10.2 instructions 2025-09-04 16:33:43 +08:00
Yongjie2017
e56130aeb5 add few missing avx10_1 instructions 2025-09-04 16:32:17 +08:00
Maciej Wieczor-Retman
1ebd820dfc insns: travis: apx: IDIV instruction
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-04 08:40:28 +02:00
Maciej Wieczor-Retman
d79e4bb93a insns: travis: apx: ENQCMD[S] instructions
Add enqcmd and enqcmds to the database.

Add relevant tests.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-04 08:40:28 +02:00
Maciej Wieczor-Retman
13b4160ec8 insns: travis: apx: DIV instruction
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-04 08:40:28 +02:00
Maciej Wieczor-Retman
e91a81d780 x86: preinsns: Fix missing vex.w bits
Looks like the wwflag variable was set for both ww and w1 which caused
some VEX.W bits to not get set. Don't set the wwflag for w0 or w1 cases
in the script.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-04 08:40:28 +02:00
Maciej Wieczor-Retman
74867b7750 insns: travis: apx: DEC instruction
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-04 08:40:28 +02:00
Maciej Wieczor-Retman
ca1228e0dd insns: travis: apx: CRC32 APX, cleanup and tests
Clean up CRC32 with $dq macro and add the APX variants.

Also add tests for legacy and APX variants.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-04 08:40:28 +02:00
Maciej Wieczor-Retman
bfb82694b7 insns: travis: apx: CMPccXADD instruction
Add CMPccXADD variant to the database with some basic testcases.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-04 08:40:28 +02:00
Maciej Wieczor-Retman
429f54a391 insns: travis: apx: CMOVcc instruction
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-04 08:40:28 +02:00
Maciej Wieczor-Retman
276b9d82b8 insns: travis: apx: Add APX extended bitmask instructions
Add APX variants of BLSI, BEXTR, BLSMSK, BLSR, BZHI.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-04 08:40:28 +02:00
Maciej Wieczor-Retman
75b5a4e1aa insns: travis: apx: ANDN instruction
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-04 08:40:28 +02:00
Maciej Wieczor-Retman
980238ae27 travis: apx: Tests for already implemted A* APX instructions
The ADD, ADC, ADCX, ADOX, AND instruction testcases.

Part of ADCX tests is commented out because addressing with R16-R31 is
currently bugged without some other mechanism indicating using the APX.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-04 08:40:28 +02:00
Maciej Wieczor-Retman
dc172d3f82 insns: travis: apx: APX support fo atomic instructions
Add the AOR instruction and use $bwdq macros on the other new atomic
instructions: AADD, AAND and AXOR.

Add tests.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-04 08:40:28 +02:00
Maciej Wieczor-Retman
89dfdc164c travis: apx: Setup test cases for apx
This json allows assembling the first column in the testcase macro when
updating the apx.bin.t file, and assembling the second column when
running the test.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-04 08:40:28 +02:00
Maciej Wieczor-Retman
1b9c2f873d x86: Immediate operand longer than byte not possible
Due to ib in the apx arithmetic instruction preprocessed implementation
only byte size immediate operands were possible. Changing ib to i# fixes
the issue.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-04 08:40:28 +02:00
H. Peter Anvin
e0d5333a47 doc: add 2.17 release notes and document [dollarhex]
Add the beginnings (at least) of release notes for 2.17, and document
the [dollarhex] directive.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-03 12:31:03 -07:00
H. Peter Anvin
d1ab9e0ae7 test/dollar.asm: check a few more cases, including %assign
Check a few more corner cases, including $ and $$, as well as parsing
in the assembler (dd) and the preprocessor (%assign).

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-03 11:48:02 -07:00
H. Peter Anvin
e80bc631a2 preproc: identify $$ as TOKEN_BASE when tokenizing
$$ is TOKEN_BASE, not a symbol. If this is done incorrectly, ppscan
chokes on $$ as it ends up being an invalid symbol.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-03 11:33:08 -07:00
H. Peter Anvin
60594fde66 Fix generation of segment references with offsets
Segment references can come from two places: either an explicit SEG
operator or from a far expression. In the former case, the segment can
have a programmer-provided offset, but in the latter case, it
cannot.

The fix for bug 3392949 fixed the latter case, but broke the
former. This patch hopefully makes both work.

Rename out_segment() to out_farseg() and add a comment to explain the
logic behind the difference.

Reported-by: E. C. Masloch <pushbx@ulukai.org>
Fixes: https://bugzilla.nasm.us/show_bug.cgi?id=3392950
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-03 11:06:16 -07:00
H. Peter Anvin
7e8f1d571e preproc: fix generation of macro invocation debug data
It is possible for m->mstk.mmac to point back to itself. In that case,
don't terminate the macro debug invocation just yet.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-03 10:34:28 -07:00
H. Peter Anvin
ece92ba533 output/legacy.c: remove stale file
output/legacy.c is no longer used, remove it.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-03 10:33:59 -07:00
H. Peter Anvin
6c105cea3b Improve misc/omfdump, add misc/Makefile, use -std=c23 if possible
- Add improvements to omfdump from Bernd Böckmann.

- Add misc/Makefile with option to install omfdump and auxiliary NASM
  data files.

- Use compiler.h and friends in the misc directory.

- Use -std=c23 if the C compiler supports it.

Cc: Bernd Boeckmann <bernd-github@boeckmann.io>
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2025-09-03 10:05:21 -07:00
H. Peter Anvin
78abbf26df asm/floats.c: micro-optimize set_bit()
Micro-optimize the set_bit() function. Using size_t (in particular,
using an unsigned type) produces better code.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-03 01:27:30 -07:00
H. Peter Anvin
38631c577a doc: there is no %fullpath() function, only %realpath()
Remove a reference to a non-existent %fullpath() function; the
function is called %realpath().

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-03 01:10:29 -07:00
H. Peter Anvin
a84925df12 $ numeric syntax: require a digit to follow
The documentation actually states that $ as a hex prefix is only valid
when followed by a digit, which at least makes the syntax conflict
less complicated. Actually match the documentation.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-03 01:05:41 -07:00
H. Peter Anvin
b3c99f9c19 doc: bump copyright year
It is 2025...

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-03 00:59:04 -07:00
H. Peter Anvin
7e46f6f7ab doc: fix a couple of syntax errors
Fix syntax errors that prevented the documentation from being
buildable.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-03 00:57:43 -07:00
H. Peter Anvin
ebfdbfc355 readnum: improve help text about deprecated $hex
State that the right thing to do is $hex -> 0xhex.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-03 00:53:16 -07:00
H. Peter Anvin
54efdde7b1 preproc: warn for leading $ when a number is consumed in preprocessor
To avoid repeated warnings, there is no warning issued for when
tokenizing a number starting with $ in the preprocessor, but issue a
warning if such a number is *consumed* (used in arithmetic) in the
preprocessor.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-03 00:46:23 -07:00
H. Peter Anvin
178a1b7443 Add directive to disable dollar-hex constants
The use of $ prefixes for hexadecimal numbers conflicts with
the use of $ to escape symbols.  Add a directive to disable
$ for hexadecimal numbers so that those escapes work OK.

As a result, allow escaped symbols to start with a digit.

Add a warning that this syntax is deprecated.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-03 00:35:41 -07:00
H. Peter Anvin
3ec5f486c6 disasm: fix VEX3 parsing, ignore immediate sizes
Immediate size annotations are irrelevant for disassembly matching.

VEX3 parsing corrected.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-02 22:22:35 -07:00