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Commit Graph

5363 Commits

Author SHA1 Message Date
H. Peter Anvin
af40cc63d2 isnsn.dat: remove unnecessary SM from PSHUF* instructions
The MMX and early SSE PSHUF* instructions were annotated SM0-1, which
is unnecessary (no ambiguity) but broke the tighter SM matching the
assembler now uses.

This is almost certainly underspecified now, but the MMX and early SSE
instruction patterns need to be tidied up anyway, and this is the
least impactful change that seems to fix the problem.

This unbreaks compiling ffmpeg.

Reported-by: Yongjie Sheng (Intel) <sheng.yongjie@outlook.com>
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-23 15:45:42 -07:00
H. Peter Anvin
ad6752e3e1 NASM 3.00rc13 nasm-3.00rc13 2025-09-23 12:14:21 -07:00
H. Peter Anvin
c0be53fc85 insns.dat: fix flags for the MSR instructions
- The MSR immediate instructions are under a separate flag
- All MSR instructions are privileged

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-23 12:12:12 -07:00
H. Peter Anvin
d782d1339f Merge remote-tracking branch 'maciej/apx.wip.for-hpa' 2025-09-23 12:01:24 -07:00
H. Peter Anvin
7e0dc756f5 doc: tidy up the APX documentation and a few other minor changes
Major tidying up of the APX chapter; do a couple of other minor fixes
in the process.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-23 12:00:31 -07:00
H. Peter Anvin
4b0a1a4539 test: simple tests for Scc syntax
Test more Scc syntax cases.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-23 11:57:58 -07:00
H. Peter Anvin
e8a0c32ba7 DFV: allow {dfv=pf} as an alias for {dfv=cf}; EQU {dfv}
PF and CF are always set to the same value; allow the programmer to
specify either or both.

Allow EQU to take a {dfv} expression without needing parens.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-23 11:56:31 -07:00
Maciej Wieczor-Retman
3edef01637 insns: avx: amx: Add missing instructions from ISE june 2025
Add all the missing instructions / instruction variants that are
specified in the 2025 June Intel ISE.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-23 18:56:26 +02:00
Maciej Wieczor-Retman
b92e1c638b insns: avx: Correct VSM4KEY4 memory operand size
Memory operand size for all VSM4KEY4 versions is specified as 128 bit
long, while the ymm register version should use 256 bit size.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-23 18:56:25 +02:00
H. Peter Anvin
010b23ae84 altreg.mac: add R16L..R31L
Add macros for the R16L-R31L aliases for the corresponding -B
registers.

The order in the file changed to put all the -L registers at the end,
to make it easier to maintain this file.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-23 09:38:28 -07:00
H. Peter Anvin
0393cf6502 doc: document that appendices C, D and E should be unchanged
Currently, the website links directly to appendix C, D, and E by name.

At some point, change the HTML generation to use the chapter names
rather than numbers.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-23 08:13:48 -07:00
Maciej Wieczor-Retman
a3191aee77 doc: apx: Document the APX syntax
Add documentation on how the new syntax elements related to APX work.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-23 16:01:30 +02:00
H. Peter Anvin
2de413db32 autoconf: more autoconf library macro updates
More macro updates from the pa_autoconf library.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
nasm-3.00rc12
2025-09-22 17:02:58 -07:00
H. Peter Anvin
8940289266 NASM 3.00rc12 2025-09-22 17:01:06 -07:00
H. Peter Anvin
c4ed07830a Tidy up the morass of EVEX bitfield constants
The EVEX bitfields are complicated at best. Tidy them up to the
best of our ability.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-20 18:26:27 -07:00
H. Peter Anvin
47c56d122e nasmlib: set of neat macros to create a useful bitfield enum
When dealing with bitmasks/bitfields, definining them in macros tends
to cause a lot of desirable constants out because it is a pain to
create all of them.  C macros can't create other macros, but they
*can* be used to create fields in an enum, so provide some neat
convenience macros for doing so.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-20 18:25:32 -07:00
H. Peter Anvin
5d75c20105 asm: drop support for ER|SAE in 256-bit vectors
An earlier version of the AVX10.2 documentation had support for ER and
SAE in 256-bit vectors using a special encoding. This was never
implemented, and has since been removed from the spec.

Remove from NASM, too.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-20 17:35:13 -07:00
Yongjie Sheng
f7f750a849 correct target operand from rm to mem only 2025-09-20 11:17:40 +08:00
H. Peter Anvin
ffad49a4fc NASM 3.00rc11 nasm-3.00rc11 2025-09-19 18:58:51 -07:00
H. Peter Anvin
c714d66d34 Fixes for JMP|CALL near, RETF, and segment instructions
Some weird things happened when macroizing.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-19 18:55:54 -07:00
H. Peter Anvin
49fba5a300 labels: can only promote a *defined* EXTERN to GLOBAL
LBL_LOCAL doesn't necessarily mean defined; have to check the defined
flag explicitly.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-19 17:01:59 -07:00
H. Peter Anvin
a0396faf3b Fix control/debug register patterns
The control and debug registers are always using the default operand
size. It is probably easiest to just encode it explicitly for now.

Control registers are particularly weird because of the AMD "lock as
REX.R" hack...

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-19 16:26:35 -07:00
H. Peter Anvin
b390ce4bb8 insns.dat: fix far jmp/call patterns
Far jmp and call are special in many ways... not the least because of
the old legacy syntax of putting the size on the segment instead of
the offset.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-19 16:06:25 -07:00
H. Peter Anvin
e2bff29935 outbin: make map file unwritable an error
If the user requests a map file, the user needs to be able to
get it!

It should have been an error, not a warning, all along.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-19 14:27:22 -07:00
H. Peter Anvin
9b18e9a913 NASM 3.00rc9 nasm-3.00rc9 2025-09-19 14:23:20 -07:00
H. Peter Anvin
d2aed9fa9d labels: handle "extern" after definition (BR 3392924)
Using "extern" or "required" after the definition should be
interpreted as "global", just as if "extern" or "required" had been
specified before the definition.

Unfortunately the code did not correctly handle the case of upgrading
from LOCAL to GLOBAL via an EXTERN or REQUIRED directive, only from
EXTERN or REQUIRED to GLOBAL via definition or a GLOBAL or COMMON
directive.

Fix.

Reported-by: E. C. Masloch <pushbx@ulukai.org>
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-19 14:22:29 -07:00
H. Peter Anvin
ca50adfb7d BR 3392957: 64-bit K registers allowed in non-64-bit mode
Do not force the operand size for K registers and "ko#"
encodings. This resolves BR 3392957.

Reported-by: ig <glucksmann@avast.com>
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-19 13:39:26 -07:00
H. Peter Anvin
8dae3d681d insns.dat: fix broken XCHG pattern (BR 3392951)
A pattern for XCHG was incompletely macroized. This caused a
fallthrough to the next pattern, reversing the operands, but would
probably have had generated incorrect code in at least some cases.

Beef up the xchg test.

Reported-by: E. C. Masloch <pushbx@ulukai.org>
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-19 12:56:19 -07:00
H. Peter Anvin
9aecb094a8 insns.dat: use explict macro flags for arithmetic flags
Instead of do more ad hoc hacks in preinsns.pl, add explicit macro
flags for the arithmetic instructions. This also allows folding CMP
back into the standard arithmetic instructions.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-19 12:28:07 -07:00
Maciej Wieczor-Retman
f0efb28d98 assemble: apx: Add NF forbidden flag and fix SBB and ADC
ADC and SBB don't support using the {nf} prefix. They are the only one
in the arithmetic instructions group that are this way.

Add a flag that will warn when an instructions wants to use {nf} but
doesnt' support it.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-19 14:53:04 +02:00
Maciej Wieczor-Retman
936cc5bbf6 insns: travis: apx: Fix msr instructions missing IMM operand
APX variants of RDMSR and WRMSRNS were missing the immediate operand.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-19 14:53:04 +02:00
H. Peter Anvin
4ad5bca94f NASM 3.00rc8 nasm-3.00rc8 2025-09-16 17:34:20 -07:00
H. Peter Anvin
537fd3fab4 portability: fix [v]snprintf() detection
To be honest, it might just be time to plain assume these, but...?

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-16 17:33:43 -07:00
H. Peter Anvin
160392a402 NASM 3.00rc7 nasm-3.00rc7 2025-09-16 15:29:24 -07:00
H. Peter Anvin
861782dc88 compiler.h: has_attribute() is broken on some gcc versions
Apparently the has_attribute() macro triggers false positives on at
least gcc 5.3, which is the version that the build server uses with
djgpp.

Drop using it, so much for trying to be standards-compliant...

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-16 15:27:34 -07:00
H. Peter Anvin
eb04e5e876 NASM 3.00rc6 nasm-3.00rc6 2025-09-16 13:27:45 -07:00
H. Peter Anvin
5e46eacc8e Merge remote-tracking branch 'yongjie/master' 2025-09-16 13:27:24 -07:00
H. Peter Anvin
55dd65cddc portability: speed and modernize autoconf; compiler.h improvements
- Add some features to autoconf that makes it cleaner and faster
- Modernize some of the autoconf macros
- Update compiler.h with some C23 features

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-16 13:25:39 -07:00
Yongjie Sheng
0a5c7e375b Update test content to reflect the fix in VINSERTxxxx and VSHUFxxxx instructions 2025-09-16 22:55:51 +08:00
Maciej Wieczor-Retman
95cf51c306 travis: apx: Fix some older todos
I missed that LZCNT can use REX2, two other TODOs were fixed by changes
made by Peter in between my patches.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-16 16:01:01 +02:00
Maciej Wieczor-Retman
f9dab2d9a1 travis: apx: PUSH[2][P] and POP[2][P] instruction tests
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-16 15:46:17 +02:00
Maciej Wieczor-Retman
ffe79d5aa5 travis: apx: SETcc tests
APX SETcc variant tests.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-16 15:33:20 +02:00
Maciej Wieczor-Retman
0fd4cff921 insns: travis: apx: CTESTcc instruction
Add the database entry for CTESTcc and the relevant test cases. The
syntax is basically CCMPSCC without two syntax variants.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-16 14:18:05 +02:00
Maciej Wieczor-Retman
2b4bc67d78 travis: apx: Separate file for legacy conditional instructions
Split off cmovcc and cmpcc to a separate file.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-16 11:31:41 +02:00
Maciej Wieczor-Retman
09c4ed6733 travis: apx: Separate files for arithmetic and bitshift instructions
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-16 11:31:13 +02:00
Maciej Wieczor-Retman
db069fe948 travis: apx: Separate files for conditional instructions
Start splitting of tests to other files because the apx.asm is getting
very big and hard to read when multiple errors happen.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-16 10:50:38 +02:00
Maciej Wieczor-Retman
b65e099cc6 travis: apx: Finish CFCMOV tests
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-16 10:39:03 +02:00
H. Peter Anvin
f6166e571a preproc: implement %hs2b() and %b2hs() functions for compact binary data
Convenience preprocessor functions that allows for efficient packing
of binary data in source code.

Move some functions that has previously been local but are more
generally useful into more accessible places.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-15 23:01:59 -07:00
H. Peter Anvin
856ac7b7fb preproc: add %chr() and %ord() string <-> byte list functions
It is sometimes just too convenient to be able to convert between
strings and bytes at will. At one point I was considering making
something with the full power of the db (et al) directives, but that
is a much bigger change...

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-15 21:48:07 -07:00
H. Peter Anvin
7b7ae6b603 travis: remove external call to hexdump
The external call to hexdump was broken and would hang if the output
exceeded the host operating system size limit. Since it *anyway*
was reading the entire dump into RAM, just rewrite it in native
Python.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-15 20:49:54 -07:00