The control and debug registers are always using the default operand
size. It is probably easiest to just encode it explicitly for now.
Control registers are particularly weird because of the AMD "lock as
REX.R" hack...
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
Far jmp and call are special in many ways... not the least because of
the old legacy syntax of putting the size on the segment instead of
the offset.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
Do not force the operand size for K registers and "ko#"
encodings. This resolves BR 3392957.
Reported-by: ig <glucksmann@avast.com>
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
A pattern for XCHG was incompletely macroized. This caused a
fallthrough to the next pattern, reversing the operands, but would
probably have had generated incorrect code in at least some cases.
Beef up the xchg test.
Reported-by: E. C. Masloch <pushbx@ulukai.org>
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
Instead of do more ad hoc hacks in preinsns.pl, add explicit macro
flags for the arithmetic instructions. This also allows folding CMP
back into the standard arithmetic instructions.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
ADC and SBB don't support using the {nf} prefix. They are the only one
in the arithmetic instructions group that are this way.
Add a flag that will warn when an instructions wants to use {nf} but
doesnt' support it.
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
Add the database entry for CTESTcc and the relevant test cases. The
syntax is basically CCMPSCC without two syntax variants.
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
The encodings of 'true' and 'false' variants of the CCMPSCC instructions
were swapped. Correct that in the preprocessor script.
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
Add database entries and test cases for WRSSD, WRSSQ, WRUSSD and WRUSSQ
instructions.
Fix whitespace in legacy database entries.
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
If the shift amount is known, there is really no reason why we can't
accept "ROLX" as an alias for "RORX" with a modified shift operand.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
These are subtle: RORX is only available in immediate shift count
form, whereas SHLX, SHRX and SARX are only available in register shift
count form...
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
Add database entries and test cases for TILELOADD, TILELOADDT1,
TILELOADDRS, TILELOADDRST1 and TILESTORED.
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
Add database entries for SHLX, SARX and SHRX (APX and non-APX). Add
tests to the newly added instructions.
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
Add test cases and the database entry for the NEG and NOT instructions.
Fix the 0xF7 variants not generating due to a missing hash sign after f6.
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
Add test cases.
Modify what I assume is a typo in the MUL clone of IMUL 0x6B. It should
only use 8bit IMM operand but the preprocessor has i# specified which
would allow other sizes too.
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
MOVRS is a pretty basic instruction; it uses the normal operand size
handling.
Fix apx.bin.t accordingly.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
KMOV opcodes of 0x90 and 0x91 have similar bits set in all size
implementations. .66 and .W1 for 32bit, and .NP and .W1 for 64 bits.
Correct my previous mistake where I swapped the VEX/EVEX.pp values by
accident.
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
