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Code Activity
5,292 Commits 61 Branches 358 Tags
a0396faf3b8bb515e37ffb51a9c5e161953cdbbf
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58 Commits

Author SHA1 Message Date
Maciej Wieczor-Retman
936cc5bbf6 insns: travis: apx: Fix msr instructions missing IMM operand 
APX variants of RDMSR and WRMSRNS were missing the immediate operand.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
 2025-09-19 14:53:04 +02:00
Maciej Wieczor-Retman
95cf51c306 travis: apx: Fix some older todos 
I missed that LZCNT can use REX2, two other TODOs were fixed by changes
made by Peter in between my patches.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
 2025-09-16 16:01:01 +02:00
Maciej Wieczor-Retman
f9dab2d9a1 travis: apx: PUSH[2][P] and POP[2][P] instruction tests 
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
 2025-09-16 15:46:17 +02:00
Maciej Wieczor-Retman
ffe79d5aa5 travis: apx: SETcc tests 
APX SETcc variant tests.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
 2025-09-16 15:33:20 +02:00
Maciej Wieczor-Retman
2b4bc67d78 travis: apx: Separate file for legacy conditional instructions 
Split off cmovcc and cmpcc to a separate file.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
 2025-09-16 11:31:41 +02:00
Maciej Wieczor-Retman
09c4ed6733 travis: apx: Separate files for arithmetic and bitshift instructions 
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
 2025-09-16 11:31:13 +02:00
Maciej Wieczor-Retman
db069fe948 travis: apx: Separate files for conditional instructions 
Start splitting of tests to other files because the apx.asm is getting
very big and hard to read when multiple errors happen.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
 2025-09-16 10:50:38 +02:00
Maciej Wieczor-Retman
b65e099cc6 travis: apx: Finish CFCMOV tests 
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
 2025-09-16 10:39:03 +02:00
Maciej Wieczor-Retman
81406e9333 Odd cfcmov behavior 
The last testcase hangs the travis test system. The cfcmovb rv rv syntax
seems to cause problems for some reason.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
 2025-09-15 19:14:19 +02:00
Maciej Wieczor-Retman
45692cfcf3 travis: apx: CCMPSCC tests 
Add a very long list of tests checking most combinations of this
instruction syntax.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
 2025-09-15 18:22:25 +02:00
Maciej Wieczor-Retman
9d1943d3b6 travis: apx: JMPABS test 
One testcase for the new APX JMPABS instruction.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
 2025-09-15 18:03:48 +02:00
Maciej Wieczor-Retman
9bc5564002 travis: apx: XOR test cases 
Add APX XOR tests.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
 2025-09-15 16:22:43 +02:00
Maciej Wieczor-Retman
fbccbfba0f insns: travis: apx: WRSSD/Q and WRUSSD/Q instructions 
Add database entries and test cases for WRSSD, WRSSQ, WRUSSD and WRUSSQ
instructions.

Fix whitespace in legacy database entries.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
 2025-09-15 16:16:26 +02:00
Maciej Wieczor-Retman
579074bc0e insns: travis: apx: WRMSRNS APX variant 
Add APX version of the WRMSRNS instruction.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
 2025-09-15 15:58:25 +02:00
Maciej Wieczor-Retman
de9f689f02 insns: travis: apx: U[RD/WR]MSR instruction 
Implement the URDMSR and UWRMSR from the ISE.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
 2025-09-15 15:48:40 +02:00
Maciej Wieczor-Retman
3b529c8c62 insns: travis: apx: Add TZCNT instruction 
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
 2025-09-12 20:29:36 +02:00
Maciej Wieczor-Retman
f6ad2553ca insns: travis: apx: Add TILELOADD[RS][T1] and TILESTORED instructions 
Add database entries and test cases for TILELOADD, TILELOADDT1,
TILELOADDRS, TILELOADDRST1 and TILESTORED.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
 2025-09-12 20:15:50 +02:00
Maciej Wieczor-Retman
3071120a5a travis: apx: Add tests for SUB instruction 
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
 2025-09-12 19:30:42 +02:00
Maciej Wieczor-Retman
2497087697 insns: travis: apx: STTILECFG instruction 
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
 2025-09-12 19:30:39 +02:00
Maciej Wieczor-Retman
e2d528a938 insns: travis: apx: SHLD and SHRD instructions 
Add database entries and test cases for SHLD and SHRD instructions.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
 2025-09-12 15:48:27 +02:00
Maciej Wieczor-Retman
70207aca5a travis: apx: Tests for SBB instruction 
Add tests in the arithmetic format for the SBB instruction.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
 2025-09-12 14:42:21 +02:00
Maciej Wieczor-Retman
0f74758bba insns: travis: apx: Shift instructions without affecting flags 
Add database entries for SHLX, SARX and SHRX (APX and non-APX). Add
tests to the newly added instructions.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
 2025-09-12 13:29:06 +02:00
Maciej Wieczor-Retman
5b9b5d0280 travis: apx: Tests for SAR/SHL/SHR 
Add tests to signed shift instructions that are APX extended.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
 2025-09-12 11:05:12 +02:00
Maciej Wieczor-Retman
bfb26ab467 insns: travis: apx: Implement RORX instruction 
Add the RORX instruction to the database - both non-APX and APX
variants.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
 2025-09-11 19:52:54 +02:00
Maciej Wieczor-Retman
fe1c9c380a insns: travis: apx: RDMSR instruction 
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
 2025-09-11 19:52:19 +02:00
Maciej Wieczor-Retman
485a09dab6 travis: apx: Test cases for rotate instructions 
Tests for RCL, RCR, ROL and ROR.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
 2025-09-11 19:02:10 +02:00
Maciej Wieczor-Retman
2ccd3a93c6 insns: travis: apx: POPCNT instruction 
The EGPRs APX case if broken, the non-APX version is used for some
reason.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
 2025-09-11 17:19:31 +02:00
Maciej Wieczor-Retman
7821dd5540 insns: travis: apx: PDEP and PEXT instruction 
Add test cases and the database entry for PDEP.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
 2025-09-11 15:56:13 +02:00
Maciej Wieczor-Retman
cbf714d742 travis: apx: OR instruction test cases 
Tests similar to other arithmetic instructions.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
 2025-09-11 14:34:40 +02:00
Maciej Wieczor-Retman
55e25b12fe insns: travis: apx: NEG and NOT legacy fix and APX variant 
Add test cases and the database entry for the NEG and NOT instructions.

Fix the 0xF7 variants not generating due to a missing hash sign after f6.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
 2025-09-11 14:23:22 +02:00
Maciej Wieczor-Retman
4d0d859dd0 insns: travis: apx: MULX instruction 
Add the APX database entry and test cases.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
 2025-09-11 14:17:32 +02:00
Maciej Wieczor-Retman
a3acacc3ad insns: travis: apx: MUL instruction 
Add test cases.

Modify what I assume is a typo in the MUL clone of IMUL 0x6B. It should
only use 8bit IMM operand but the preprocessor has i# specified which
would allow other sizes too.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
 2025-09-11 14:17:32 +02:00
Maciej Wieczor-Retman
ed290acf80 insns: travis: apx: APX MOVRS instruction 
Add the APX database entry for MOVRS and relevant test cases.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
 2025-09-11 14:17:32 +02:00
Maciej Wieczor-Retman
30eb8e2e2a insns: travis: apx: MOVRS instruction 
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
 2025-09-05 23:25:42 +02:00
Maciej Wieczor-Retman
beaeb77bce insns: travis: apx: MOVDIR instructions 
Add MOVDIR64B and MOVDIRI to the database. Add relevant testcases

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
 2025-09-05 23:25:20 +02:00
Maciej Wieczor-Retman
05a07b7ccf insns: travis: apx: MOVBE instruction 
Add the database entry and test cases.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
 2025-09-05 21:44:57 +02:00
Maciej Wieczor-Retman
712095fffe insns: travis: apx: LZCNT instruction 
Doesn't yet work with EGPRs.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
 2025-09-05 17:23:29 +02:00
Maciej Wieczor-Retman
ca85c1c3b5 insns: travis: apx: LDTILECFG instruction 
Add database entry and test cases.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
 2025-09-05 16:02:58 +02:00
Maciej Wieczor-Retman
3b3a115754 travis: apx: Finish the KMOV test cases 
Add remaining APX versions of the KMOV tests (kmovw - kmovq)

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
 2025-09-05 15:19:36 +02:00
Maciej Wieczor-Retman
1054b5aefc x86: Fix handling of the ko# specifier 
KMOV opcodes of 0x90 and 0x91 have similar bits set in all size
implementations. .66 and .W1 for 32bit, and .NP and .W1 for 64 bits.

Correct my previous mistake where I swapped the VEX/EVEX.pp values by
accident.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
 2025-09-05 15:17:05 +02:00
Maciej Wieczor-Retman
fca408f86a travis: apx: Remove a TODO comment 
The problems got fixed at 3.0rc0.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
 2025-09-05 11:10:38 +02:00
Maciej Wieczor-Retman
e30047b2ff x86: travis: apx: Fix IMUL 0x6B not being able to use EVEX.ZU 
64bit and 32bit variant of the IMUL 0x6B instruction can't make use of
the zero-upper bit. It gets assembled normally. With equal operand size
this makes sense since 64 and 32 bit legacy behavior was the same as the
APX ZU one. But the 0x6B IMUL variant uses 8 bit immediate values as the
second operand, hence it should be able to make use of ZU for 32 and 64
bit registers too.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
 2025-09-05 11:05:57 +02:00
Maciej Wieczor-Retman
5d1deaffc3 WIP apx: KMOV instructions 
Add KMOV APX variants to the database. Add relevant tests.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
 2025-09-04 23:35:14 +02:00
Maciej Wieczor-Retman
3387f868fd insns: travis: apx: INV instruction 
Add INVPCI, INVEPT, INVVPID APX instruction variants to the database and
relevant tests.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
 2025-09-04 23:29:21 +02:00
Maciej Wieczor-Retman
cb453cba39 insns: travis: apx: INC instruction 
Add INC test cases and the database entry.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
 2025-09-04 13:33:06 +02:00
Maciej Wieczor-Retman
6b137d5212 insns: travis: apx: IMUL instruction test cases and bug fix 
Add the test cases for the IMUL instruction.

Fix the 0x6B database bug that used the same bit width of the immediate
operand as the other operands. Make it 8 bit wide, just like in the
legacy instruction.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
 2025-09-04 13:13:12 +02:00
Maciej Wieczor-Retman
1ebd820dfc insns: travis: apx: IDIV instruction 
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
 2025-09-04 08:40:28 +02:00
Maciej Wieczor-Retman
d79e4bb93a insns: travis: apx: ENQCMD[S] instructions 
Add enqcmd and enqcmds to the database.

Add relevant tests.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
 2025-09-04 08:40:28 +02:00
Maciej Wieczor-Retman
13b4160ec8 insns: travis: apx: DIV instruction 
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
 2025-09-04 08:40:28 +02:00
Maciej Wieczor-Retman
74867b7750 insns: travis: apx: DEC instruction 
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
 2025-09-04 08:40:28 +02:00