0
0
mirror of https://github.com/netwide-assembler/nasm.git synced 2025-09-22 10:43:39 -04:00
Commit Graph

5292 Commits

Author SHA1 Message Date
H. Peter Anvin
a0396faf3b Fix control/debug register patterns
The control and debug registers are always using the default operand
size. It is probably easiest to just encode it explicitly for now.

Control registers are particularly weird because of the AMD "lock as
REX.R" hack...

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-19 16:26:35 -07:00
H. Peter Anvin
b390ce4bb8 insns.dat: fix far jmp/call patterns
Far jmp and call are special in many ways... not the least because of
the old legacy syntax of putting the size on the segment instead of
the offset.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-19 16:06:25 -07:00
H. Peter Anvin
e2bff29935 outbin: make map file unwritable an error
If the user requests a map file, the user needs to be able to
get it!

It should have been an error, not a warning, all along.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-19 14:27:22 -07:00
H. Peter Anvin
9b18e9a913 NASM 3.00rc9 nasm-3.00rc9 2025-09-19 14:23:20 -07:00
H. Peter Anvin
d2aed9fa9d labels: handle "extern" after definition (BR 3392924)
Using "extern" or "required" after the definition should be
interpreted as "global", just as if "extern" or "required" had been
specified before the definition.

Unfortunately the code did not correctly handle the case of upgrading
from LOCAL to GLOBAL via an EXTERN or REQUIRED directive, only from
EXTERN or REQUIRED to GLOBAL via definition or a GLOBAL or COMMON
directive.

Fix.

Reported-by: E. C. Masloch <pushbx@ulukai.org>
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-19 14:22:29 -07:00
H. Peter Anvin
ca50adfb7d BR 3392957: 64-bit K registers allowed in non-64-bit mode
Do not force the operand size for K registers and "ko#"
encodings. This resolves BR 3392957.

Reported-by: ig <glucksmann@avast.com>
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-19 13:39:26 -07:00
H. Peter Anvin
8dae3d681d insns.dat: fix broken XCHG pattern (BR 3392951)
A pattern for XCHG was incompletely macroized. This caused a
fallthrough to the next pattern, reversing the operands, but would
probably have had generated incorrect code in at least some cases.

Beef up the xchg test.

Reported-by: E. C. Masloch <pushbx@ulukai.org>
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-19 12:56:19 -07:00
H. Peter Anvin
9aecb094a8 insns.dat: use explict macro flags for arithmetic flags
Instead of do more ad hoc hacks in preinsns.pl, add explicit macro
flags for the arithmetic instructions. This also allows folding CMP
back into the standard arithmetic instructions.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-19 12:28:07 -07:00
Maciej Wieczor-Retman
f0efb28d98 assemble: apx: Add NF forbidden flag and fix SBB and ADC
ADC and SBB don't support using the {nf} prefix. They are the only one
in the arithmetic instructions group that are this way.

Add a flag that will warn when an instructions wants to use {nf} but
doesnt' support it.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-19 14:53:04 +02:00
Maciej Wieczor-Retman
936cc5bbf6 insns: travis: apx: Fix msr instructions missing IMM operand
APX variants of RDMSR and WRMSRNS were missing the immediate operand.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-19 14:53:04 +02:00
H. Peter Anvin
4ad5bca94f NASM 3.00rc8 nasm-3.00rc8 2025-09-16 17:34:20 -07:00
H. Peter Anvin
537fd3fab4 portability: fix [v]snprintf() detection
To be honest, it might just be time to plain assume these, but...?

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-16 17:33:43 -07:00
H. Peter Anvin
160392a402 NASM 3.00rc7 nasm-3.00rc7 2025-09-16 15:29:24 -07:00
H. Peter Anvin
861782dc88 compiler.h: has_attribute() is broken on some gcc versions
Apparently the has_attribute() macro triggers false positives on at
least gcc 5.3, which is the version that the build server uses with
djgpp.

Drop using it, so much for trying to be standards-compliant...

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-16 15:27:34 -07:00
H. Peter Anvin
eb04e5e876 NASM 3.00rc6 nasm-3.00rc6 2025-09-16 13:27:45 -07:00
H. Peter Anvin
5e46eacc8e Merge remote-tracking branch 'yongjie/master' 2025-09-16 13:27:24 -07:00
H. Peter Anvin
55dd65cddc portability: speed and modernize autoconf; compiler.h improvements
- Add some features to autoconf that makes it cleaner and faster
- Modernize some of the autoconf macros
- Update compiler.h with some C23 features

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-16 13:25:39 -07:00
Yongjie Sheng
0a5c7e375b Update test content to reflect the fix in VINSERTxxxx and VSHUFxxxx instructions 2025-09-16 22:55:51 +08:00
Maciej Wieczor-Retman
95cf51c306 travis: apx: Fix some older todos
I missed that LZCNT can use REX2, two other TODOs were fixed by changes
made by Peter in between my patches.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-16 16:01:01 +02:00
Maciej Wieczor-Retman
f9dab2d9a1 travis: apx: PUSH[2][P] and POP[2][P] instruction tests
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-16 15:46:17 +02:00
Maciej Wieczor-Retman
ffe79d5aa5 travis: apx: SETcc tests
APX SETcc variant tests.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-16 15:33:20 +02:00
Maciej Wieczor-Retman
0fd4cff921 insns: travis: apx: CTESTcc instruction
Add the database entry for CTESTcc and the relevant test cases. The
syntax is basically CCMPSCC without two syntax variants.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-16 14:18:05 +02:00
Maciej Wieczor-Retman
2b4bc67d78 travis: apx: Separate file for legacy conditional instructions
Split off cmovcc and cmpcc to a separate file.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-16 11:31:41 +02:00
Maciej Wieczor-Retman
09c4ed6733 travis: apx: Separate files for arithmetic and bitshift instructions
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-16 11:31:13 +02:00
Maciej Wieczor-Retman
db069fe948 travis: apx: Separate files for conditional instructions
Start splitting of tests to other files because the apx.asm is getting
very big and hard to read when multiple errors happen.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-16 10:50:38 +02:00
Maciej Wieczor-Retman
b65e099cc6 travis: apx: Finish CFCMOV tests
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-16 10:39:03 +02:00
H. Peter Anvin
f6166e571a preproc: implement %hs2b() and %b2hs() functions for compact binary data
Convenience preprocessor functions that allows for efficient packing
of binary data in source code.

Move some functions that has previously been local but are more
generally useful into more accessible places.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-15 23:01:59 -07:00
H. Peter Anvin
856ac7b7fb preproc: add %chr() and %ord() string <-> byte list functions
It is sometimes just too convenient to be able to convert between
strings and bytes at will. At one point I was considering making
something with the full power of the db (et al) directives, but that
is a much bigger change...

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-15 21:48:07 -07:00
H. Peter Anvin
7b7ae6b603 travis: remove external call to hexdump
The external call to hexdump was broken and would hang if the output
exceeded the host operating system size limit. Since it *anyway*
was reading the entire dump into RAM, just rewrite it in native
Python.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-15 20:49:54 -07:00
H. Peter Anvin
42795e59a7 Merge remote-tracking branch 'maciej/apx.wip.travis' 2025-09-15 20:06:57 -07:00
H. Peter Anvin
ab55dfb5b2 autoconf: fix test for S_ISREG(), tidy up stat tests
S_ISREG() is usually a macro, it needs PA_HAVE_FUNC().
Don't bother checking for functions related to struct _stati64 if that
definition doesn't exist.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-15 20:02:01 -07:00
H. Peter Anvin
dc247c9f99 Speed up autoconf, use POSIX names instead of cpu_to_le*()
The POSIX names for these functions are htole*(). Use those
preferentially.

Speed up autoconf by allowing early-out during alternative function
searches.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-15 18:26:25 -07:00
H. Peter Anvin
3ea17cb2f8 Merge commit '4a5bc1cec672240515d04e15bbcb7b58a50c23b0' 2025-09-15 13:04:34 -07:00
H. Peter Anvin
53fe1a132c Merge remote-tracking branch 'yongjie/master' 2025-09-15 13:00:26 -07:00
Maciej Wieczor-Retman
81406e9333 Odd cfcmov behavior
The last testcase hangs the travis test system. The cfcmovb rv rv syntax
seems to cause problems for some reason.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-15 19:14:19 +02:00
Maciej Wieczor-Retman
eb25e7ab8e insns: CFCMOVcc
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-15 19:07:43 +02:00
Maciej Wieczor-Retman
45692cfcf3 travis: apx: CCMPSCC tests
Add a very long list of tests checking most combinations of this
instruction syntax.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-15 18:22:25 +02:00
Maciej Wieczor-Retman
4a5bc1cec6 insns: Fix ccmpscc T/F encoding
The encodings of 'true' and 'false' variants of the CCMPSCC instructions
were swapped. Correct that in the preprocessor script.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-15 18:05:15 +02:00
Maciej Wieczor-Retman
9d1943d3b6 travis: apx: JMPABS test
One testcase for the new APX JMPABS instruction.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-15 18:03:48 +02:00
Maciej Wieczor-Retman
9bc5564002 travis: apx: XOR test cases
Add APX XOR tests.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-15 16:22:43 +02:00
Maciej Wieczor-Retman
fbccbfba0f insns: travis: apx: WRSSD/Q and WRUSSD/Q instructions
Add database entries and test cases for WRSSD, WRSSQ, WRUSSD and WRUSSQ
instructions.

Fix whitespace in legacy database entries.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-15 16:16:26 +02:00
Yongjie Sheng
737d8bc6d0 remove VINSERT and VSHUFF due to duplication and missing v for VINSET 2025-09-15 22:05:48 +08:00
Maciej Wieczor-Retman
579074bc0e insns: travis: apx: WRMSRNS APX variant
Add APX version of the WRMSRNS instruction.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-15 15:58:25 +02:00
Maciej Wieczor-Retman
de9f689f02 insns: travis: apx: U[RD/WR]MSR instruction
Implement the URDMSR and UWRMSR from the ISE.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-15 15:48:40 +02:00
H. Peter Anvin
75f7e2bfa6 doc: remove & used for list
Using & for a list is not consistent with the style elsewhere.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-14 23:52:22 -07:00
H. Peter Anvin
a25bc0a5d4 doc: fix broken section heading for DEFAULT BND
The section heading for DEFAULT BND was broken (missing \); make the
tags saner, too.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-14 23:50:43 -07:00
H. Peter Anvin
1ea955f981 doc: add "backwards" to "%if, compatibility" index entries
It is much clearer so, and it still fits.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-14 04:35:56 -07:00
H. Peter Anvin
1284cb15d9 NASM 3.00rc5 nasm-3.00rc5 2025-09-14 04:32:49 -07:00
H. Peter Anvin
31c4d8bcfd doc: describe caveat with old NASM and new %if directives
Older versions of NASM would not try to match unknown %if directives
with a corresponding %endif, resulting in some very odd consequences
when it comes to trying to handle support for multiple NASM versions.

Document the problem.

Reported-by: E. C. Masloch <pushbx@ulukai.org>
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2025-09-14 04:07:19 -07:00
H. Peter Anvin
1f1f3266d6 preproc: look for what looks to be an unknown conditional
If an unknown preprocessor directive starting with %if or %elif is
encountered, assume it should be treated as a conditional directive
for the purpose of balancing %if...%endif.

This avoids some really ugly problems when dealing with code that is
intended to work across NASM versions that uses %if directives that
don't yet exist.

Reported-by: E. C. Masloch <pushbx@ulukai.org>
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-14 03:25:26 -07:00