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Commit Graph

351 Commits

Author SHA1 Message Date
redzimski
94c6ecda5b fix [warning push] causing "unknown warning name"
[warning push] emitted a "unknown warning name" warning when
-w+unknown-warning is set.
2025-11-04 10:23:54 -08:00
H. Peter Anvin (Intel)
94923e1382 travis: improve the RET instruction test
Split the RET instruction test by mode for ease of disassembly, and
test more subcases.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-10-15 22:51:34 -07:00
H. Peter Anvin (Intel)
4709cfe493 Show instruction mismatch errors if another error terminates assembly
Instruction mismatch errors have been held until the last assembly
pass in case changed %if statements cause a code path to be elided in
subsequent passes. However, it is confusing to the user if error
messages aren't shown if another error terminates assembly.

Use the already existing mechanism for warnings to hold the messages
unless another error terminates assembly.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-10-15 22:32:36 -07:00
H. Peter Anvin
ca67f50341 travis: unbreak the ret.asm test
The ret.asm test was broken because the assembly expected -DERROR=1
whereas the run script provided -DERROR, masking all the actual
errors...

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-10-15 22:32:32 -07:00
H. Peter Anvin
bf16907c9d travis: unbreak the ret.asm test
The ret.asm test was broken because the assembly expected -DERROR=1
whereas the run script provided -DERROR, masking all the actual
errors...

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-10-15 22:29:01 -07:00
H. Peter Anvin
1a907c27a5 travis: always generate a list file; show subtest number
Always generate a list file and point output at a given filename, even
if failure is expected.

Remove ad hoc -o output names that generally don't point into safe
locations.

The result is that the preprocessing options (-E) no longer output to
stdout, so change the tests accordingly.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-10-15 22:11:09 -07:00
H. Peter Anvin (Intel)
a7457e66cf Fix matching of branch instructions with prefixes and sizes
Matching of branch instructions with prefixes and sizes is, to say the
least, tricky. Work through it, and add a new macro to help.

Fixes: https://github.com/netwide-assembler/nasm/issues/144
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-10-10 13:07:46 -07:00
H. Peter Anvin (Intel)
2c71e67762 travis: don't stop on failure
Don't stop travis after a single test failure. It is better to run all
the tests and get a comprehensive list of failing tests.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-10-10 10:55:11 -07:00
H. Peter Anvin (Intel)
5a6b276b89 travis: make travis output list files for debugging
It is so much easier to debug problems with a list file in hand.
Generate them, always.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-10-09 22:28:34 -07:00
InstLatx64
378ee0e9c5 AMX-TRANSPOSE: removed, retag instructions NEVER.
All the 16 AMX-TRANSPOSE instructions were removed from the 59th
edition of "Intel Architecture Instruction Set Extensions and Future
Features Programming Reference" September 2025, 319433-059.

Similar to PCOMMIT, they are tagged as 'NEVER'

[ hpa: don't remove from tests, but suppress the warnings.  Don't
  remove the CPUID tag; a future version of NASM will actually implement
  CPU filtering based on the various CPUID tags; that development is
  genuinely in progress. ]

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-10-09 14:44:24 -07:00
H. Peter Anvin (Intel)
51dce26137 travis improvements: look for python3, log output, option to filter
Use autoconf to find either python3 or python.

Add option to travis to filter the contents of stdout or stderr.

Generate the _version.stdout travis matching file from the version
file.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-10-08 12:56:00 -07:00
H. Peter Anvin (Intel)
a398a41f0a travis: update AMX test
Update AMX test per previous commit from IntLatx64.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-10-08 11:59:23 -07:00
H. Peter Anvin
6df250aee3 parser: add the actual name of a label to the label-orphan warning
The label-orphan warning is *way* more useful if it includes the
actual label name; this way the programmer can usually spot
immediately if it is a label or misspelled instruction.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-10-07 08:30:02 -07:00
H. Peter Anvin
b3358fe63e insns.dat: reinstate TEST reg,mem alias
Officially the syntax for TEST is "rm,reg"; however TEST is
commutative in every aspect, and as such "reg,mem" is an equivalent
form that NASM has also supported in the past.

Reinstate it properly.

Fixes: https://bugzilla.nasm.us/show_bug.cgi?id=3392962
Reported-by: E. C. Masloch <pushbx@ulukai.org>
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-10-06 13:07:09 -07:00
H. Peter Anvin
d9958f428a test/exitrep: test for proper %if and %rep evaluation suppression
If a line is suppressed, the %if or %rep condition must never be
evaluated. Test for it, and add the exitrep test to travis.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-10-06 09:38:55 -07:00
Yongjie Sheng
95095b325c add few more avx10.2 convert instructions 2025-09-30 23:29:30 +08:00
Sheng, Yongjie
f350ad1f4b Update vmovd and vmovw operand sequence 2025-09-30 15:34:08 +01:00
Sheng, Yongjie
4e7fdc1d62 update travis test for vextract instruction family 2025-09-30 14:47:10 +01:00
H. Peter Anvin
12f6270124 asm: better error messages for missing instructions
The assembler can't know if something is a colonless label or a
misspelled instruction, so print both when complaining about a missing
instruction.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-29 16:09:04 -07:00
Yongjie Sheng
8ce0504457 update instruction VP2INTERSECT 2025-09-24 22:12:45 +08:00
Yongjie Sheng
d12a5b5156 add instruction VBCSTNEBF162PS 2025-09-24 21:09:36 +08:00
Yongjie Sheng
e548c76ab3 add AMX instruction TDPFP16PS 2025-09-24 19:52:27 +08:00
Yongjie Sheng
8a30c94a09 add aes key locker instructions 2025-09-24 11:25:51 +08:00
H. Peter Anvin
8dae3d681d insns.dat: fix broken XCHG pattern (BR 3392951)
A pattern for XCHG was incompletely macroized. This caused a
fallthrough to the next pattern, reversing the operands, but would
probably have had generated incorrect code in at least some cases.

Beef up the xchg test.

Reported-by: E. C. Masloch <pushbx@ulukai.org>
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-19 12:56:19 -07:00
Maciej Wieczor-Retman
f0efb28d98 assemble: apx: Add NF forbidden flag and fix SBB and ADC
ADC and SBB don't support using the {nf} prefix. They are the only one
in the arithmetic instructions group that are this way.

Add a flag that will warn when an instructions wants to use {nf} but
doesnt' support it.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-19 14:53:04 +02:00
Maciej Wieczor-Retman
936cc5bbf6 insns: travis: apx: Fix msr instructions missing IMM operand
APX variants of RDMSR and WRMSRNS were missing the immediate operand.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-19 14:53:04 +02:00
H. Peter Anvin
5e46eacc8e Merge remote-tracking branch 'yongjie/master' 2025-09-16 13:27:24 -07:00
Yongjie Sheng
0a5c7e375b Update test content to reflect the fix in VINSERTxxxx and VSHUFxxxx instructions 2025-09-16 22:55:51 +08:00
Maciej Wieczor-Retman
95cf51c306 travis: apx: Fix some older todos
I missed that LZCNT can use REX2, two other TODOs were fixed by changes
made by Peter in between my patches.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-16 16:01:01 +02:00
Maciej Wieczor-Retman
f9dab2d9a1 travis: apx: PUSH[2][P] and POP[2][P] instruction tests
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-16 15:46:17 +02:00
Maciej Wieczor-Retman
ffe79d5aa5 travis: apx: SETcc tests
APX SETcc variant tests.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-16 15:33:20 +02:00
Maciej Wieczor-Retman
0fd4cff921 insns: travis: apx: CTESTcc instruction
Add the database entry for CTESTcc and the relevant test cases. The
syntax is basically CCMPSCC without two syntax variants.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-16 14:18:05 +02:00
Maciej Wieczor-Retman
2b4bc67d78 travis: apx: Separate file for legacy conditional instructions
Split off cmovcc and cmpcc to a separate file.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-16 11:31:41 +02:00
Maciej Wieczor-Retman
09c4ed6733 travis: apx: Separate files for arithmetic and bitshift instructions
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-16 11:31:13 +02:00
Maciej Wieczor-Retman
db069fe948 travis: apx: Separate files for conditional instructions
Start splitting of tests to other files because the apx.asm is getting
very big and hard to read when multiple errors happen.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-16 10:50:38 +02:00
Maciej Wieczor-Retman
b65e099cc6 travis: apx: Finish CFCMOV tests
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-16 10:39:03 +02:00
H. Peter Anvin
7b7ae6b603 travis: remove external call to hexdump
The external call to hexdump was broken and would hang if the output
exceeded the host operating system size limit. Since it *anyway*
was reading the entire dump into RAM, just rewrite it in native
Python.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-15 20:49:54 -07:00
Maciej Wieczor-Retman
81406e9333 Odd cfcmov behavior
The last testcase hangs the travis test system. The cfcmovb rv rv syntax
seems to cause problems for some reason.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-15 19:14:19 +02:00
Maciej Wieczor-Retman
45692cfcf3 travis: apx: CCMPSCC tests
Add a very long list of tests checking most combinations of this
instruction syntax.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-15 18:22:25 +02:00
Maciej Wieczor-Retman
9d1943d3b6 travis: apx: JMPABS test
One testcase for the new APX JMPABS instruction.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-15 18:03:48 +02:00
Maciej Wieczor-Retman
9bc5564002 travis: apx: XOR test cases
Add APX XOR tests.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-15 16:22:43 +02:00
Maciej Wieczor-Retman
fbccbfba0f insns: travis: apx: WRSSD/Q and WRUSSD/Q instructions
Add database entries and test cases for WRSSD, WRSSQ, WRUSSD and WRUSSQ
instructions.

Fix whitespace in legacy database entries.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-15 16:16:26 +02:00
Maciej Wieczor-Retman
579074bc0e insns: travis: apx: WRMSRNS APX variant
Add APX version of the WRMSRNS instruction.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-15 15:58:25 +02:00
Maciej Wieczor-Retman
de9f689f02 insns: travis: apx: U[RD/WR]MSR instruction
Implement the URDMSR and UWRMSR from the ISE.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-15 15:48:40 +02:00
H. Peter Anvin
c719835357 Officially deprecate implicit DEFAULT ABS, add DEFAULT [FS|GS]:[ABS|REL]
Making DEFAULT ABS the default for 64-bit mode was a real
mistake. Issue a warning so we can eventually change it.

Support making FS: and GS: references also be REL by default.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-13 23:15:47 -07:00
H. Peter Anvin
9aa48acb3e Merge remote-tracking branch 'yongjie/master' 2025-09-13 20:10:04 -07:00
Yongjie Sheng
87e28e26bd add the remaining missing avx10.1 instructions 2025-09-14 07:15:12 +08:00
Yongjie Sheng
ef4128783f tune VCMPPH instruction and its travis test 2025-09-13 20:28:42 +08:00
Yongjie Sheng
7e304ade60 tune VADDPH instruction and its travis test 2025-09-13 14:23:20 +08:00
Yongjie Sheng
e7a3279828 add avx10_2 instruction VPDPWxxxx family and AVX10_VNNIINT flag 2025-09-13 09:05:56 +08:00