Looks like the wwflag variable was set for both ww and w1 which caused
some VEX.W bits to not get set. Don't set the wwflag for w0 or w1 cases
in the script.
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
Clean up CRC32 with $dq macro and add the APX variants.
Also add tests for legacy and APX variants.
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
Add the AOR instruction and use $bwdq macros on the other new atomic
instructions: AADD, AAND and AXOR.
Add tests.
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
Due to ib in the apx arithmetic instruction preprocessed implementation
only byte size immediate operands were possible. Changing ib to i# fixes
the issue.
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
KMOV with GPR size encodings are "special"; the encoding matches neither
the K register size encodings nor the APX ones. In the end it seems
that the most straightforward is simply to hand-code the B and W
patterns.
The disassembler still breaks horribly on these patterns....
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
NOP disassembly is a little "special" because it sits as part of the
XCHG instructions. Add a flag to bail out of the disassembler search
early, and ignore the 0330 bytecode.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
Fix the handling of instruction patterns for KMOV and KUNPCK.
Don't allow K-less versions of KTEST and KORTEST because of
fundmentally different semantics.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
The semantics for KTEST are so very different from TEST that it would
be a bad idea to allow the TEST spelling.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
If VEX.V is an immediate, it should not be subject to register range
checks.
If the WW flag is set, REX_W needs to be OR'd in, not XOR'd, because
the map might have the W bit set for matching purposes.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
- Significantly overhauled the disassembler internals to make
better use of the information already in the instruction template
and to reduce the implementation differences with the assembler
- Add APX support to the disassembler
- Fix problem with disassembler truncating addresses of jumps
- Fix generation of invalid EAs in 16-bit mode
- Fix array overrun for types in a few modules
- Fix invalid ND flag on near JMP
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
- rex2.w is used as a opcode extension (JMPABS), not rex2.x1 as an
earlier version of the spec had.
- Segment prefixes used as Jcc hints are valid in 64-bit mode.
- Avoid duplicate warning messages for ignored/invalid prefixes.
* emit_prefixes() is called twice during code generation.
- Add the UDB #UD opcode in 64-bit mode; SALC is 16/32-bit only.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
Add a Perl script to try to automate REX2 compatibility flagging. Not
yet integrated into the build process.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
Add a optimization frameword for operand narrowing (where the operand
size doesn't matter beyond a certain range because only certain bits
are referenced.)
Add a macro *and* matching facility for dealing with segment selectors, which are
typically rm16/r32/r64, but exactly how that is applied varies
depending on if a datum is read or written.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
Add the MOVBE CPUID flag, add helper patterns for 16-bit BSWAP
emulation. Unfortunately using ROL/ROR for registers other than the
ones for which XCHG can work clobbers the flags.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
More work on cleaning up instruction patterns, fixing matchig corner
cases, and tidying up the organization of insns.dat.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
More matching and macrofication work.
Improve some error and warning messages.
Update some travis tests for better messages and added optimizations.
Fix duplicated warning messages for the same out-of-range value
problem.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
Tag pseudo-instructions explicitly and don't set any CPU level flag
for those.
Change insnsa.c to have (length, pointer) rather than using an ever
increasing in size sentinel at the end of each table. This also means
that empty tables (Dx, INCBIN) can be omitted entirely.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Add more instruction macros and fix problems. Adjust some matching
problems.
Remove all FUTURE tags from the instruction list, and add a bunch of
new CPUID tags. Hopefully a small step toward actually getting CPU
feature selection working properly in the future.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
"nw" now means: 64-bit operand size is the default, o32 is not
permitted in 64-bit mode.
"osz" means: instruction size determined by prefixes, otherwise the
mode default.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Don't break a string on a quoted comma, for obvious reasons. Allow an
op argument to be quoted in general.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Add more improvements to the macro features. Now it is possible to
generate the -X versions of the shift instructions as part of the
macroization, which is highly desirable in order to allow them to be
generated using {nf} syntax.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Work more on the macro facility. Add the ability to kill an
instruction pattern based on expansion (if the token KILL appears.)
Add APX patterns to the arithmetic macro and macroize the shift and
rotate patterns.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Make the macro facility in preinsns.pl more general, and relying less
on evaluating Perl constructs. This *might* be practical with some
more work, to move to a data file, but wait until we have a better
idea of the needs.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
The former addflags.pl now does more general preprocessing, so rename
it from addflags.pl to preinsns.pl.
To generate the instruction list in the documentation, use the
post-preprocessed insns.xda file.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
