The control and debug registers are always using the default operand
size. It is probably easiest to just encode it explicitly for now.
Control registers are particularly weird because of the AMD "lock as
REX.R" hack...
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
Do not force the operand size for K registers and "ko#"
encodings. This resolves BR 3392957.
Reported-by: ig <glucksmann@avast.com>
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
Instead of do more ad hoc hacks in preinsns.pl, add explicit macro
flags for the arithmetic instructions. This also allows folding CMP
back into the standard arithmetic instructions.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
ADC and SBB don't support using the {nf} prefix. They are the only one
in the arithmetic instructions group that are this way.
Add a flag that will warn when an instructions wants to use {nf} but
doesnt' support it.
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
These are subtle: RORX is only available in immediate shift count
form, whereas SHLX, SHRX and SARX are only available in register shift
count form...
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
64bit and 32bit variant of the IMUL 0x6B instruction can't make use of
the zero-upper bit. It gets assembled normally. With equal operand size
this makes sense since 64 and 32 bit legacy behavior was the same as the
APX ZU one. But the 0x6B IMUL variant uses 8 bit immediate values as the
second operand, hence it should be able to make use of ZU for 32 and 64
bit registers too.
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
Looks like the wwflag variable was set for both ww and w1 which caused
some VEX.W bits to not get set. Don't set the wwflag for w0 or w1 cases
in the script.
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
Due to ib in the apx arithmetic instruction preprocessed implementation
only byte size immediate operands were possible. Changing ib to i# fixes
the issue.
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
Fix the handling of instruction patterns for KMOV and KUNPCK.
Don't allow K-less versions of KTEST and KORTEST because of
fundmentally different semantics.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
The semantics for KTEST are so very different from TEST that it would
be a bad idea to allow the TEST spelling.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
Add a optimization frameword for operand narrowing (where the operand
size doesn't matter beyond a certain range because only certain bits
are referenced.)
Add a macro *and* matching facility for dealing with segment selectors, which are
typically rm16/r32/r64, but exactly how that is applied varies
depending on if a datum is read or written.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
More work on cleaning up instruction patterns, fixing matchig corner
cases, and tidying up the organization of insns.dat.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
More matching and macrofication work.
Improve some error and warning messages.
Update some travis tests for better messages and added optimizations.
Fix duplicated warning messages for the same out-of-range value
problem.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
Add more instruction macros and fix problems. Adjust some matching
problems.
Remove all FUTURE tags from the instruction list, and add a bunch of
new CPUID tags. Hopefully a small step toward actually getting CPU
feature selection working properly in the future.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
"nw" now means: 64-bit operand size is the default, o32 is not
permitted in 64-bit mode.
"osz" means: instruction size determined by prefixes, otherwise the
mode default.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Don't break a string on a quoted comma, for obvious reasons. Allow an
op argument to be quoted in general.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Add more improvements to the macro features. Now it is possible to
generate the -X versions of the shift instructions as part of the
macroization, which is highly desirable in order to allow them to be
generated using {nf} syntax.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Work more on the macro facility. Add the ability to kill an
instruction pattern based on expansion (if the token KILL appears.)
Add APX patterns to the arithmetic macro and macroize the shift and
rotate patterns.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Make the macro facility in preinsns.pl more general, and relying less
on evaluating Perl constructs. This *might* be practical with some
more work, to move to a data file, but wait until we have a better
idea of the needs.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
The former addflags.pl now does more general preprocessing, so rename
it from addflags.pl to preinsns.pl.
To generate the instruction list in the documentation, use the
post-preprocessed insns.xda file.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
