-- TCMMIMFP16PS, TCMMRLFP16PS instructions
-- AMX.asm fix: Similar to GATHER instructions, 3-operand AMX instructions cannot have the same operand more than once
Checked with XED version: [v2025.06.08]
Add all the missing instructions / instruction variants that are
specified in the 2025 June Intel ISE.
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
ADC and SBB don't support using the {nf} prefix. They are the only one
in the arithmetic instructions group that are this way.
Add a flag that will warn when an instructions wants to use {nf} but
doesnt' support it.
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
NOP disassembly is a little "special" because it sits as part of the
XCHG instructions. Add a flag to bail out of the disassembler search
early, and ignore the 0330 bytecode.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
If VEX.V is an immediate, it should not be subject to register range
checks.
If the WW flag is set, REX_W needs to be OR'd in, not XOR'd, because
the map might have the W bit set for matching purposes.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
- rex2.w is used as a opcode extension (JMPABS), not rex2.x1 as an
earlier version of the spec had.
- Segment prefixes used as Jcc hints are valid in 64-bit mode.
- Avoid duplicate warning messages for ignored/invalid prefixes.
* emit_prefixes() is called twice during code generation.
- Add the UDB #UD opcode in 64-bit mode; SALC is 16/32-bit only.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
Add the MOVBE CPUID flag, add helper patterns for 16-bit BSWAP
emulation. Unfortunately using ROL/ROR for registers other than the
ones for which XCHG can work clobbers the flags.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
More work on cleaning up instruction patterns, fixing matchig corner
cases, and tidying up the organization of insns.dat.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
Tag pseudo-instructions explicitly and don't set any CPU level flag
for those.
Change insnsa.c to have (length, pointer) rather than using an ever
increasing in size sentinel at the end of each table. This also means
that empty tables (Dx, INCBIN) can be omitted entirely.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Add more instruction macros and fix problems. Adjust some matching
problems.
Remove all FUTURE tags from the instruction list, and add a bunch of
new CPUID tags. Hopefully a small step toward actually getting CPU
feature selection working properly in the future.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
This is a WIP checkpoint; not all tests pass yet.
More matching changes, and hopefully something much closer to what
really is desired now. The number of required patterns is now much
smaller.
However, a lot of *changes* are needed to the patterns.
Since some patterns are repeated all over the place, clean up the
x86/addflags.pl script and make it able to generate macro-based
common patterns; first use being the patterns for the "basic 8"
arithmetic patterns.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Work through a number of changes toward making matching a lot saner,
both to reduce the number of patterns to generate for APX but also to
make a number of code patterns simpler.
This replaces a fair number of byte codes.
Improve a number of error messages, especially related to overflows.
Move process_insn() from nasm.c to assemble.c, as it really is the
primary entry point to the assembler module.
Reorder some prefixes. In particular, F2/F3 override 66 when used as a
mandatory prefix, so it makes more sense for them to be closer to the
opcode.
Move a lot more information into struct insn. It is better to have it
in one place; memory consumption is not an issue because struct insn
is transient information.
Get rid of "optimization levels" and replace it with a mask of
flags. That was already halfway done; complete the job.
Replace seg:offset in struct out_data with a struct location. It would
be better to extend this to more places, too.
The ARx and SMx flags are now explicit bitmasks, instead of having a
couple of hard-coded ranges.
Add __func__ to assert or panic messages.
Because of prefix and message changes, a number of travis tests had to
be audited and updated.
Fix a number of instruction patterns which had .128 when they ought to
be .lig. This is no longer a minor issue with the disassembler: for
AVX10, the pattern vector length determines how SAE/RC are encoded,
and there is no valid 128-bit encoding. However, with .lig the 512-bit
encoding can be used.
Separate "o64nw" into two pieces: opsize 64 and "nw" = "REX.w not necessary". The
latter can be included in non-64-bit patterns. "o64" still set REX.W
since that is still the common thing.
New "osz" bytecode: emit an OSP *or* REX.W depending on the current
mode and operand size. Useful for special cases like "nop" where "o64
nop" probably wants to be encoded as "48 90".
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Merge a bunch of common code in the handling of modr/m
generation. Make the handing of compressed disp8 simpler and more
transparent by exporting a the shift factor for the compressed
immediate in ea_data. For the case of no compression, the shift factor
is simply 0; there is no need to distinguish "compressed" from
"uncompressed".
The tidied up version of the disp8 code is simple enough that it makes
more sense to inline it.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
The {nf} and {zu} prefixes (or suffixes) can be used on a number of
instructions without actually change the encodings (either they don't
touch the flags at all, or they write a 32- or 64-bit register
already.)
Make this a bit more flexible, by adding an FL instruction flag for
the instructions which actually touch the flags, and a ZU instruction
flag for the instructions which zero the upper half.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Change the byte code format and the byte code compiler to be able to
generate various kinds of APX-format instructions.
THE NEW BYTE CODES ARE NOT YET IMPLEMENTED IN THE ASSEMBLER OR
DISASSEMBLER.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Change the handling of {dfv=} to a more general "braced constant"
expression, to be tagged with an instruction flag to make sure they
match the instruction in question.
This really ought to be an operand flag, but the opflags are precious;
as the CCMP/CTEST instructions can also take an immediate it probably
is necessary to invent a "special immediate" operand type that can
fold these together.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Add support for VEX-encoded SHA512-NI instructions.
Signed-off-by: Tomasz Kantecki <tomasz.kantecki@intel.com>
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Kind of embarrassing... I had not implemented the FRED instruction,
despite personally being one of the architects of FRED ;)
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
"LOCK XCHG reg,mem" would issue a warning for being unlockable, which
is incorrect. In this case the RM encoding is simply an alias for the
MR encoding. Add a "LOCK1" bit to deal with that.
However, XCHG is *always* locked, so create a new warning to
explicitly flag a user-specified LOCK XCHG; default off.
Consider optimizing that prefix away in the future, but for now, let's
stick to the user-requested code sequence.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
For VEX instructions created *after* the corresponding EVEX
instructions, we need the user to either explicitly declare them {vex}
or specifying "cpu latevex".
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Add vector instructions from the Intel Instruction Set Extensions
document, version 046, September 2022.
Still need to check for missing instructions that have already passed
through the ISE into the SDM.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Additional nonvector instructions from the Intel Instruction Set
Extensions document 319433-046 September 2022.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Instead of handling conditional instructions ad hoc, generate
individual instruction patterns as normal. This simplifies the code
and makes CMPccXADD support simpler (otherwise it would be necessary
to hack in the handling of a condition code in the middle of an
instruction.)
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Add support for AVX512-FP16 instructions and the associated
handling. Allow "mapN" syntax as well as "mN" syntax to match the
documentation.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
BNDMK, BNDLDX, and BNDSTX are split-SIB (MIB) instructions, but do
*not* require a SIB encoding. However, TILELOAD* and TILESTORE* *do*
require a SIB in all cases. Split the MIB flag into MIB (split
address) and SIB (SIB required) flags.
This fixes travis test mpx.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
Add instructions for Intel Control Flow Enforcement Technology (CET).
Signed-off-by: Henrik Gramner <henrik@gramner.com>
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
The memory operand size of LEA doesn't matter in any way as it isn't
"real memory". Add an ANYSIZE option to ignore sizes entirely.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
Distinguish instructions which have once been valid (OBSOLETE) from
those that never saw the light of day (NEVER). Futhermore, flag
instructions which devolve to an architectural noop from those with
undefined behavior and possibly recycled opcodes.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
Add file missing from commit 418138c8f2:
iflags: move definitions to a separate file; auto-generate more
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
