Improve the byte code reference documentation to make a few opcodes
more clear and add some general properties about the byte codes,
including the files that need to be changed when the byte code
changes.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
The operand size prefix byte code (o#) was missing in the CMPXCHG
pattern.
Reported-by: Yongjie Sheng <sheng.yongjie@intel.com>
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
Don't stop travis after a single test failure. It is better to run all
the tests and get a comprehensive list of failing tests.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
Quoted strings should be valid inside directives, including ones that
contain a ] character. Also check for garbage on the line after the
directive.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
If the assembly stops after the first pass, only active_list_options
will be seen; this is also the value that applies for local changes in
the list options. Thus, both variables need to be tweaked.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
The o64, a64 and a16 prefixes are only possible in specific
modes. It is a lot easier to debug with a more sensible error message.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
The prefix/suffix directive documentation were missing some brackets,
lost in the course of editing.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
`a || b` only evaluates b if a is false. `a | b` always evaluates
both a and b. If a and b are of type bool, || is usually what you
want, so clang now warns on `|` where both arguments are of type bool.
This warning fires once in nasm. It looks like `|` is an (inconsequential)
typo of `||`, so use that instead.
No intended behavior change.
Not all registers are valid as memory references, and thus
using RM_ZERO is incorrect. Use RN_ZERO instead, which is simply the
zero-register bit.
Fixes: https://github.com/netwide-assembler/nasm/issues/140
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
[ hpa: added comment that "rm" really is a WMAKE internal command. ]
Signed-off-by: KO Myung-Hun <komh78@gmail.com>
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
Open Watcom does not support 64-bit constants at 'case'.
[ hpa: I'm pulling this, but I'm really, *really* questioning its
supportability long term. The OpenWatcom people need to fix this, or
we are just going to have to say "OW is not supported."
At some point we *are* going to move to a "C99 is baseline" policy for
code; there are simply too many features in C99 that are actively
painful to be without.
That is, unless we decide to go to C++, which is under consideration
but is a much bigger job. In that case, the target will probably be
either C++11 or C++14 as those C++ versions contain some pretty
essential features. ]
Signed-off-by: KO Myung-Hun <komh78@gmail.com>
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
For the benefit of those platforms which have to rely on VPATH, avoid
having the same filename in multiple subdirectories.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
All the 16 AMX-TRANSPOSE instructions were removed from the 59th
edition of "Intel Architecture Instruction Set Extensions and Future
Features Programming Reference" September 2025, 319433-059.
Similar to PCOMMIT, they are tagged as 'NEVER'
[ hpa: don't remove from tests, but suppress the warnings. Don't
remove the CPUID tag; a future version of NASM will actually implement
CPU filtering based on the various CPUID tags; that development is
genuinely in progress. ]
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
Use autoconf to find either python3 or python.
Add option to travis to filter the contents of stdout or stderr.
Generate the _version.stdout travis matching file from the version
file.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
-- AMX instruction fixes
-- AMX test file extension with new levels
according to Intel ISA Extension Guide 58th edition
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
Make the spellings for the label-mangling options and pragmas
consistent, and implement the directive forms which were documented
but never implemented.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
The shift and rotate patterns are "interesting" in the following way:
1. Even though only 4/5/6 bits of the input are ever used, for the
regular instructions the input is specified as the CL register, but
for the -X instructions as a size-matching register. This makes the
optimization patterns "interesting."
2. The sequencing of legacy, VEX -X versions, APX EVEX, and APX -X
For #1, allow any size register to contain the shift count.
For #2, split up the macro generation of the patterns, and add a new
"$xmacro" macro to deal with the combinatorics of generating all the
-X patterns. Written directly in Perl since it seemed easier than
trying to make anything more general for what is very much a special
case...
Reported-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
Most instructions support contracted forms, but those had been overlooked.
Signed-off-by: Henrik Gramner <henrik@gramner.com>
[ hpa: manual merge ]
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
The rounding specifier should be applied to src2, not src1.
Furthermore, VCVTSI2SD with a 32-bit source operand does not
support specifying a rounding mode (as no rounding can occur).
Signed-off-by: Henrik Gramner <henrik@gramner.com>
[ hpa: manual merge ]
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
"suffix" is the more common English term, but NASM used "postfix" for
a long time. Allow them as aliases, and tidy up the documentation
accordingly. While making these changes, tidy up the handling of
options in the index.
Fixes: https://github.com/netwide-assembler/nasm/pull/61
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
According to the June edition of SDM evex-form of the VCVTPS2PH command only exists with mmmmm equal to 0f38, and map5 only exists for the VCVTPS2PHX command
