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mirror of https://github.com/netwide-assembler/nasm.git synced 2025-10-10 00:25:06 -04:00
Commit Graph

5270 Commits

Author SHA1 Message Date
Maciej Wieczor-Retman
2b4bc67d78 travis: apx: Separate file for legacy conditional instructions
Split off cmovcc and cmpcc to a separate file.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-16 11:31:41 +02:00
Maciej Wieczor-Retman
09c4ed6733 travis: apx: Separate files for arithmetic and bitshift instructions
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-16 11:31:13 +02:00
Maciej Wieczor-Retman
db069fe948 travis: apx: Separate files for conditional instructions
Start splitting of tests to other files because the apx.asm is getting
very big and hard to read when multiple errors happen.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-16 10:50:38 +02:00
Maciej Wieczor-Retman
b65e099cc6 travis: apx: Finish CFCMOV tests
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-16 10:39:03 +02:00
H. Peter Anvin
f6166e571a preproc: implement %hs2b() and %b2hs() functions for compact binary data
Convenience preprocessor functions that allows for efficient packing
of binary data in source code.

Move some functions that has previously been local but are more
generally useful into more accessible places.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-15 23:01:59 -07:00
H. Peter Anvin
856ac7b7fb preproc: add %chr() and %ord() string <-> byte list functions
It is sometimes just too convenient to be able to convert between
strings and bytes at will. At one point I was considering making
something with the full power of the db (et al) directives, but that
is a much bigger change...

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-15 21:48:07 -07:00
H. Peter Anvin
7b7ae6b603 travis: remove external call to hexdump
The external call to hexdump was broken and would hang if the output
exceeded the host operating system size limit. Since it *anyway*
was reading the entire dump into RAM, just rewrite it in native
Python.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-15 20:49:54 -07:00
H. Peter Anvin
42795e59a7 Merge remote-tracking branch 'maciej/apx.wip.travis' 2025-09-15 20:06:57 -07:00
H. Peter Anvin
ab55dfb5b2 autoconf: fix test for S_ISREG(), tidy up stat tests
S_ISREG() is usually a macro, it needs PA_HAVE_FUNC().
Don't bother checking for functions related to struct _stati64 if that
definition doesn't exist.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-15 20:02:01 -07:00
H. Peter Anvin
dc247c9f99 Speed up autoconf, use POSIX names instead of cpu_to_le*()
The POSIX names for these functions are htole*(). Use those
preferentially.

Speed up autoconf by allowing early-out during alternative function
searches.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-15 18:26:25 -07:00
H. Peter Anvin
3ea17cb2f8 Merge commit '4a5bc1cec672240515d04e15bbcb7b58a50c23b0' 2025-09-15 13:04:34 -07:00
H. Peter Anvin
53fe1a132c Merge remote-tracking branch 'yongjie/master' 2025-09-15 13:00:26 -07:00
Maciej Wieczor-Retman
81406e9333 Odd cfcmov behavior
The last testcase hangs the travis test system. The cfcmovb rv rv syntax
seems to cause problems for some reason.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-15 19:14:19 +02:00
Maciej Wieczor-Retman
eb25e7ab8e insns: CFCMOVcc
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-15 19:07:43 +02:00
Maciej Wieczor-Retman
45692cfcf3 travis: apx: CCMPSCC tests
Add a very long list of tests checking most combinations of this
instruction syntax.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-15 18:22:25 +02:00
Maciej Wieczor-Retman
4a5bc1cec6 insns: Fix ccmpscc T/F encoding
The encodings of 'true' and 'false' variants of the CCMPSCC instructions
were swapped. Correct that in the preprocessor script.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-15 18:05:15 +02:00
Maciej Wieczor-Retman
9d1943d3b6 travis: apx: JMPABS test
One testcase for the new APX JMPABS instruction.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-15 18:03:48 +02:00
Maciej Wieczor-Retman
9bc5564002 travis: apx: XOR test cases
Add APX XOR tests.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-15 16:22:43 +02:00
Maciej Wieczor-Retman
fbccbfba0f insns: travis: apx: WRSSD/Q and WRUSSD/Q instructions
Add database entries and test cases for WRSSD, WRSSQ, WRUSSD and WRUSSQ
instructions.

Fix whitespace in legacy database entries.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-15 16:16:26 +02:00
Yongjie Sheng
737d8bc6d0 remove VINSERT and VSHUFF due to duplication and missing v for VINSET 2025-09-15 22:05:48 +08:00
Maciej Wieczor-Retman
579074bc0e insns: travis: apx: WRMSRNS APX variant
Add APX version of the WRMSRNS instruction.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-15 15:58:25 +02:00
Maciej Wieczor-Retman
de9f689f02 insns: travis: apx: U[RD/WR]MSR instruction
Implement the URDMSR and UWRMSR from the ISE.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-15 15:48:40 +02:00
H. Peter Anvin
75f7e2bfa6 doc: remove & used for list
Using & for a list is not consistent with the style elsewhere.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-14 23:52:22 -07:00
H. Peter Anvin
a25bc0a5d4 doc: fix broken section heading for DEFAULT BND
The section heading for DEFAULT BND was broken (missing \); make the
tags saner, too.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-14 23:50:43 -07:00
H. Peter Anvin
1ea955f981 doc: add "backwards" to "%if, compatibility" index entries
It is much clearer so, and it still fits.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-14 04:35:56 -07:00
H. Peter Anvin
1284cb15d9 NASM 3.00rc5 nasm-3.00rc5 2025-09-14 04:32:49 -07:00
H. Peter Anvin
31c4d8bcfd doc: describe caveat with old NASM and new %if directives
Older versions of NASM would not try to match unknown %if directives
with a corresponding %endif, resulting in some very odd consequences
when it comes to trying to handle support for multiple NASM versions.

Document the problem.

Reported-by: E. C. Masloch <pushbx@ulukai.org>
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2025-09-14 04:07:19 -07:00
H. Peter Anvin
1f1f3266d6 preproc: look for what looks to be an unknown conditional
If an unknown preprocessor directive starting with %if or %elif is
encountered, assume it should be treated as a conditional directive
for the purpose of balancing %if...%endif.

This avoids some really ugly problems when dealing with code that is
intended to work across NASM versions that uses %if directives that
don't yet exist.

Reported-by: E. C. Masloch <pushbx@ulukai.org>
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-14 03:25:26 -07:00
H. Peter Anvin
f43845f160 stdmac: fix __?NASM_IFDIRECTIVE?__ -> __?NASM_HAS_IFDIRECTIVE?__
The intended form was __?NASM_HAS_IFDIRECTIVE?__, which matches the
documentation but not the code. Fix the code.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-14 02:54:35 -07:00
H. Peter Anvin
7276cfde99 preproc: remove the message-generating functions
The message-generating functions appear to get expanded when they
shouldn't, resulting in errors. Disable them for now and remove them
from the documentation.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-14 02:48:58 -07:00
H. Peter Anvin
84115eeca6 preproc: add %find() and %findi() functions
Add the %find() and %findi() functions to look for a string in a
list. This is useful with picking apart the contents of the
__?DEFAULT?__ macro, for example.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-14 01:24:42 -07:00
H. Peter Anvin
4ccdf7e6fe preproc: add __?DEFAULT?__ macro representing the DEFAULT settings
Create a __?DEFAULT?__ magic macro with the settings of the DEFAULT
directive.

The DEFAULT directive is complex enough that this is best done with a
magic macro.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-14 00:38:50 -07:00
H. Peter Anvin
c719835357 Officially deprecate implicit DEFAULT ABS, add DEFAULT [FS|GS]:[ABS|REL]
Making DEFAULT ABS the default for 64-bit mode was a real
mistake. Issue a warning so we can eventually change it.

Support making FS: and GS: references also be REL by default.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-13 23:15:47 -07:00
H. Peter Anvin
014ca9fdb3 doc: document the %exitmacro directive
The %exitmacro directive was never documented, apparently...

Reported-by: E. C. Masloch <pushbx@ulukai.org>
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2025-09-13 21:47:05 -07:00
H. Peter Anvin
53c2f24c3d doc: 3.0 -> 3.00; tidy up the language for __?NASM_HAS_IFDIRECTIVE?__
Change 3.0 to 3.00 in all version numbers, since NASM has
traditionally expanded all but the major version number to 2 digits.

Make the language related to __?NASM_HAS_IFDIRECTIVE?__ more
consistent.

Reported-by: E. C. Masloch <pushbx@ulukai.org>
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-13 21:35:06 -07:00
H. Peter Anvin
c77549231f NASM 3.00rc4 nasm-3.00rc4 2025-09-13 21:26:13 -07:00
H. Peter Anvin
04c21dc0c5 Allow synthesis of ROLX
If the shift amount is known, there is really no reason why we can't
accept "ROLX" as an alias for "RORX" with a modified shift operand.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-13 21:25:02 -07:00
H. Peter Anvin
01cef66b23 insns.dat/preinsns.pl: fix the RORX, SHLX, SHRX, SARX patterns
These are subtle: RORX is only available in immediate shift count
form, whereas SHLX, SHRX and SARX are only available in register shift
count form...

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-13 20:44:53 -07:00
H. Peter Anvin
9aa48acb3e Merge remote-tracking branch 'yongjie/master' 2025-09-13 20:10:04 -07:00
Yongjie Sheng
87e28e26bd add the remaining missing avx10.1 instructions 2025-09-14 07:15:12 +08:00
Yongjie Sheng
ef4128783f tune VCMPPH instruction and its travis test 2025-09-13 20:28:42 +08:00
Yongjie Sheng
7e304ade60 tune VADDPH instruction and its travis test 2025-09-13 14:23:20 +08:00
Yongjie Sheng
e7a3279828 add avx10_2 instruction VPDPWxxxx family and AVX10_VNNIINT flag 2025-09-13 09:05:56 +08:00
Maciej Wieczor-Retman
3b529c8c62 insns: travis: apx: Add TZCNT instruction
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-12 20:29:36 +02:00
Maciej Wieczor-Retman
f6ad2553ca insns: travis: apx: Add TILELOADD[RS][T1] and TILESTORED instructions
Add database entries and test cases for TILELOADD, TILELOADDT1,
TILELOADDRS, TILELOADDRST1 and TILESTORED.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-12 20:15:50 +02:00
Maciej Wieczor-Retman
3071120a5a travis: apx: Add tests for SUB instruction
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-12 19:30:42 +02:00
Maciej Wieczor-Retman
2497087697 insns: travis: apx: STTILECFG instruction
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-12 19:30:39 +02:00
Maciej Wieczor-Retman
e2d528a938 insns: travis: apx: SHLD and SHRD instructions
Add database entries and test cases for SHLD and SHRD instructions.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-12 15:48:27 +02:00
Maciej Wieczor-Retman
70207aca5a travis: apx: Tests for SBB instruction
Add tests in the arithmetic format for the SBB instruction.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-12 14:42:21 +02:00
Maciej Wieczor-Retman
0f74758bba insns: travis: apx: Shift instructions without affecting flags
Add database entries for SHLX, SARX and SHRX (APX and non-APX). Add
tests to the newly added instructions.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-12 13:29:06 +02:00