Looks like the wwflag variable was set for both ww and w1 which caused
some VEX.W bits to not get set. Don't set the wwflag for w0 or w1 cases
in the script.
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
Clean up CRC32 with $dq macro and add the APX variants.
Also add tests for legacy and APX variants.
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
The ADD, ADC, ADCX, ADOX, AND instruction testcases.
Part of ADCX tests is commented out because addressing with R16-R31 is
currently bugged without some other mechanism indicating using the APX.
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
Add the AOR instruction and use $bwdq macros on the other new atomic
instructions: AADD, AAND and AXOR.
Add tests.
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
This json allows assembling the first column in the testcase macro when
updating the apx.bin.t file, and assembling the second column when
running the test.
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
Due to ib in the apx arithmetic instruction preprocessed implementation
only byte size immediate operands were possible. Changing ib to i# fixes
the issue.
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
Check a few more corner cases, including $ and $$, as well as parsing
in the assembler (dd) and the preprocessor (%assign).
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
$$ is TOKEN_BASE, not a symbol. If this is done incorrectly, ppscan
chokes on $$ as it ends up being an invalid symbol.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
Segment references can come from two places: either an explicit SEG
operator or from a far expression. In the former case, the segment can
have a programmer-provided offset, but in the latter case, it
cannot.
The fix for bug 3392949 fixed the latter case, but broke the
former. This patch hopefully makes both work.
Rename out_segment() to out_farseg() and add a comment to explain the
logic behind the difference.
Reported-by: E. C. Masloch <pushbx@ulukai.org>
Fixes: https://bugzilla.nasm.us/show_bug.cgi?id=3392950
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
It is possible for m->mstk.mmac to point back to itself. In that case,
don't terminate the macro debug invocation just yet.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
- Add improvements to omfdump from Bernd Böckmann.
- Add misc/Makefile with option to install omfdump and auxiliary NASM
data files.
- Use compiler.h and friends in the misc directory.
- Use -std=c23 if the C compiler supports it.
Cc: Bernd Boeckmann <bernd-github@boeckmann.io>
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Micro-optimize the set_bit() function. Using size_t (in particular,
using an unsigned type) produces better code.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
The documentation actually states that $ as a hex prefix is only valid
when followed by a digit, which at least makes the syntax conflict
less complicated. Actually match the documentation.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
To avoid repeated warnings, there is no warning issued for when
tokenizing a number starting with $ in the preprocessor, but issue a
warning if such a number is *consumed* (used in arithmetic) in the
preprocessor.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
The use of $ prefixes for hexadecimal numbers conflicts with
the use of $ to escape symbols. Add a directive to disable
$ for hexadecimal numbers so that those escapes work OK.
As a result, allow escaped symbols to start with a digit.
Add a warning that this syntax is deprecated.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
IP-relative values, both jump addresses and RIP-relative memory
addressing, are relative to the end of the instruction.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
- Correct the parsing of VEX map numbers
- Strip the size bits from register names that don't have
intrinsic size
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
KMOV with GPR size encodings are "special"; the encoding matches neither
the K register size encodings nor the APX ones. In the end it seems
that the most straightforward is simply to hand-code the B and W
patterns.
The disassembler still breaks horribly on these patterns....
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
NOP disassembly is a little "special" because it sits as part of the
XCHG instructions. Add a flag to bail out of the disassembler search
early, and ignore the 0330 bytecode.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
Fix the handling of instruction patterns for KMOV and KUNPCK.
Don't allow K-less versions of KTEST and KORTEST because of
fundmentally different semantics.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
The semantics for KTEST are so very different from TEST that it would
be a bad idea to allow the TEST spelling.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
For a symbol to start with $, it needs to be escaped with a second
dollar sign: $$. This was not handled correctly, instead $$ was seen
as TOKEN_BASE.
Fix this.
Reported-by: E. C. Masloch <pushbx@ulukai.org>
Fixes: https://bugzilla.nasm.us/show_bug.cgi?id=3392922
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
An x86 instruction can be up to 15 bytes long + WAIT
pseudo-prefix. Add an option to make the hex dump wide enough to
accommodate all 16 possible bytes.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
With these changes, the disassembler correctly decodes the ccmp.asm
and apx.asm tests.
Fix rebuilding the main tools from test/Makefile.in.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
If VEX.V is an immediate, it should not be subject to register range
checks.
If the WW flag is set, REX_W needs to be OR'd in, not XOR'd, because
the map might have the W bit set for matching purposes.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
With ndisasm now built separately, make it easier to explicitly make
nasm and ndisasm from the test directory.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
- Significantly overhauled the disassembler internals to make
better use of the information already in the instruction template
and to reduce the implementation differences with the assembler
- Add APX support to the disassembler
- Fix problem with disassembler truncating addresses of jumps
- Fix generation of invalid EAs in 16-bit mode
- Fix array overrun for types in a few modules
- Fix invalid ND flag on near JMP
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
- rex2.w is used as a opcode extension (JMPABS), not rex2.x1 as an
earlier version of the spec had.
- Segment prefixes used as Jcc hints are valid in 64-bit mode.
- Avoid duplicate warning messages for ignored/invalid prefixes.
* emit_prefixes() is called twice during code generation.
- Add the UDB #UD opcode in 64-bit mode; SALC is 16/32-bit only.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
Factor the objects ONLY needed for the disassembler into a
separate library. This allows building the assembler even while
the disassembler is not yet buildable; this makes working on
the disassembler easier.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
