When using the internal zlib, need to make sure to add the appropriate
-I option for the header...
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
MOVRS is a pretty basic instruction; it uses the normal operand size
handling.
Fix apx.bin.t accordingly.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
There are currently six variations of each conditionals, and there may
be more in the future (e.g. %while). Stop trying to enumerate them all
everywhere.
Add support for index copying in the document processor.
Have pptok.pl auto-generate index metadata for conditional
preprocessor directives.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
Define a __?NASM_HAS_IFDIRECTIVE?__ to know when it is safe to use
%ifdirective and other dynamic probing features.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
Make it a little easier to run bench tests which include multiple bit
sizes, and add the SRC define to make SRC/BIN tests easier to run on
the bench.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
Make the handling of messages saner. In particular, regularize the
handling of info and debug messages, so that nasm_info() and
nasm_debug() actually become useful.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
KMOV opcodes of 0x90 and 0x91 have similar bits set in all size
implementations. .66 and .W1 for 32bit, and .NP and .W1 for 64 bits.
Correct my previous mistake where I swapped the VEX/EVEX.pp values by
accident.
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
The 66 prefix on these instructions are an opcode extension prefix,
not an operand prefix, so use w# to set the size rather than o#.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
This bit needs to be masked *except* when:
- There is no V operand
- The modr/m has mod == 3 OR there is an scc
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
Fix the handling of legacy map prefixes (0F, 0F 38, 0F 3A).
Fix 8-bit GPRs decoding (REX vs no-REX versions.)
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
64bit and 32bit variant of the IMUL 0x6B instruction can't make use of
the zero-upper bit. It gets assembled normally. With equal operand size
this makes sense since 64 and 32 bit legacy behavior was the same as the
APX ZU one. But the 0x6B IMUL variant uses 8 bit immediate values as the
second operand, hence it should be able to make use of ZU for 32 and 64
bit registers too.
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
JMPABS does not need .w1 and in fact is documented to NOT have or
require it.
Add jump-over emulation for the !APX case, similar to the jump-over
for long conditional branches in < 386.
Move JMP ABS patterns ahead of regular jumps; otherwise JMP ABS syntax
doesn't work.
Prefer JMPABS in the disassembler, since that is the documented form.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
JMPABS is defined as REX2 + A1; there are no extra encoding bits.
MOVABS is only supported without REX2; since there are no register
numbers used for that instruction that is good enough.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
It seems to make sense to call this upcoming release NASM 3.0.
Suggested by: Yongjie Sheng <sheng.yongjie@intel.com>
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
Some new warnings, some duplicate warnings removed.
The selfref test was broken because of mishandling of $ escaped
symbols; the new set of error messages are far more correct.
With all of this, travis now passes again.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
The crc32 test now does produce the correct output one would expect
for running with optimized assembly.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
The CRC32 byte patterns are documented to be able to take a
(pointless) REX.W to "extend" the pattern to a 64-bit
destination... but that never changes the result.
However, be excrutiatingly correct and add those patterns when not
using optimization.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
The crc32 instructions are kind of odd; the operand size really only
applies to the right (source) operand.
The APX forms are also kind of messy.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
Update the apx.bin.t file, since it now produces the same output as it
does with -DSRC and -DBIN.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
Memory references should have RN_L16 set if and only if they are
compatible with instruction patterns requiring register numbers below
16.
Add a "vex+" encoding pattern for VEX-encoded instructions that should
be promoted to EVEX when AVX-encoded.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
If there are no labels in the default segment, then NASM would crash
if anything was emitted in it, as the label would be defined on the
final pass only.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
Along with C and other languages, the current trend is to be able to
probe for features rather than relying on version numbers. This is
motivated in part by the intent of bumping the major version number to
3.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
Add the %null(), %note(), %warning(), %error(), and %fatal()
functions. They behave like the corresponding directives, then expands
to nothing.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
Add INVPCI, INVEPT, INVVPID APX instruction variants to the database and
relevant tests.
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
Add the test cases for the IMUL instruction.
Fix the 0x6B database bug that used the same bit width of the immediate
operand as the other operands. Make it 8 bit wide, just like in the
legacy instruction.
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
