If the shift amount is known, there is really no reason why we can't
accept "ROLX" as an alias for "RORX" with a modified shift operand.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
These are subtle: RORX is only available in immediate shift count
form, whereas SHLX, SHRX and SARX are only available in register shift
count form...
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
Add database entries and test cases for TILELOADD, TILELOADDT1,
TILELOADDRS, TILELOADDRST1 and TILESTORED.
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
Add database entries for SHLX, SARX and SHRX (APX and non-APX). Add
tests to the newly added instructions.
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
Add test cases and the database entry for the NEG and NOT instructions.
Fix the 0xF7 variants not generating due to a missing hash sign after f6.
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
Add test cases.
Modify what I assume is a typo in the MUL clone of IMUL 0x6B. It should
only use 8bit IMM operand but the preprocessor has i# specified which
would allow other sizes too.
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
MOVRS is a pretty basic instruction; it uses the normal operand size
handling.
Fix apx.bin.t accordingly.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
KMOV opcodes of 0x90 and 0x91 have similar bits set in all size
implementations. .66 and .W1 for 32bit, and .NP and .W1 for 64 bits.
Correct my previous mistake where I swapped the VEX/EVEX.pp values by
accident.
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
The 66 prefix on these instructions are an opcode extension prefix,
not an operand prefix, so use w# to set the size rather than o#.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
64bit and 32bit variant of the IMUL 0x6B instruction can't make use of
the zero-upper bit. It gets assembled normally. With equal operand size
this makes sense since 64 and 32 bit legacy behavior was the same as the
APX ZU one. But the 0x6B IMUL variant uses 8 bit immediate values as the
second operand, hence it should be able to make use of ZU for 32 and 64
bit registers too.
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
JMPABS does not need .w1 and in fact is documented to NOT have or
require it.
Add jump-over emulation for the !APX case, similar to the jump-over
for long conditional branches in < 386.
Move JMP ABS patterns ahead of regular jumps; otherwise JMP ABS syntax
doesn't work.
Prefer JMPABS in the disassembler, since that is the documented form.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
JMPABS is defined as REX2 + A1; there are no extra encoding bits.
MOVABS is only supported without REX2; since there are no register
numbers used for that instruction that is good enough.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
The CRC32 byte patterns are documented to be able to take a
(pointless) REX.W to "extend" the pattern to a 64-bit
destination... but that never changes the result.
However, be excrutiatingly correct and add those patterns when not
using optimization.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
The crc32 instructions are kind of odd; the operand size really only
applies to the right (source) operand.
The APX forms are also kind of messy.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
Memory references should have RN_L16 set if and only if they are
compatible with instruction patterns requiring register numbers below
16.
Add a "vex+" encoding pattern for VEX-encoded instructions that should
be promoted to EVEX when AVX-encoded.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
Along with C and other languages, the current trend is to be able to
probe for features rather than relying on version numbers. This is
motivated in part by the intent of bumping the major version number to
3.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
Add INVPCI, INVEPT, INVVPID APX instruction variants to the database and
relevant tests.
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
Add the test cases for the IMUL instruction.
Fix the 0x6B database bug that used the same bit width of the immediate
operand as the other operands. Make it 8 bit wide, just like in the
legacy instruction.
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
