Making DEFAULT ABS the default for 64-bit mode was a real
mistake. Issue a warning so we can eventually change it.
Support making FS: and GS: references also be REL by default.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
Add database entries and test cases for TILELOADD, TILELOADDT1,
TILELOADDRS, TILELOADDRST1 and TILESTORED.
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
Add database entries for SHLX, SARX and SHRX (APX and non-APX). Add
tests to the newly added instructions.
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
Add test cases and the database entry for the NEG and NOT instructions.
Fix the 0xF7 variants not generating due to a missing hash sign after f6.
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
Add test cases.
Modify what I assume is a typo in the MUL clone of IMUL 0x6B. It should
only use 8bit IMM operand but the preprocessor has i# specified which
would allow other sizes too.
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
MOVRS is a pretty basic instruction; it uses the normal operand size
handling.
Fix apx.bin.t accordingly.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
KMOV opcodes of 0x90 and 0x91 have similar bits set in all size
implementations. .66 and .W1 for 32bit, and .NP and .W1 for 64 bits.
Correct my previous mistake where I swapped the VEX/EVEX.pp values by
accident.
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
64bit and 32bit variant of the IMUL 0x6B instruction can't make use of
the zero-upper bit. It gets assembled normally. With equal operand size
this makes sense since 64 and 32 bit legacy behavior was the same as the
APX ZU one. But the 0x6B IMUL variant uses 8 bit immediate values as the
second operand, hence it should be able to make use of ZU for 32 and 64
bit registers too.
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
Some new warnings, some duplicate warnings removed.
The selfref test was broken because of mishandling of $ escaped
symbols; the new set of error messages are far more correct.
With all of this, travis now passes again.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
The crc32 test now does produce the correct output one would expect
for running with optimized assembly.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
Update the apx.bin.t file, since it now produces the same output as it
does with -DSRC and -DBIN.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
Add INVPCI, INVEPT, INVVPID APX instruction variants to the database and
relevant tests.
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
Add the test cases for the IMUL instruction.
Fix the 0x6B database bug that used the same bit width of the immediate
operand as the other operands. Make it 8 bit wide, just like in the
legacy instruction.
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
Clean up CRC32 with $dq macro and add the APX variants.
Also add tests for legacy and APX variants.
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
