If the shift amount is known, there is really no reason why we can't
accept "ROLX" as an alias for "RORX" with a modified shift operand.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
Segment references can come from two places: either an explicit SEG
operator or from a far expression. In the former case, the segment can
have a programmer-provided offset, but in the latter case, it
cannot.
The fix for bug 3392949 fixed the latter case, but broke the
former. This patch hopefully makes both work.
Rename out_segment() to out_farseg() and add a comment to explain the
logic behind the difference.
Reported-by: E. C. Masloch <pushbx@ulukai.org>
Fixes: https://bugzilla.nasm.us/show_bug.cgi?id=3392950
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
The use of $ prefixes for hexadecimal numbers conflicts with
the use of $ to escape symbols. Add a directive to disable
$ for hexadecimal numbers so that those escapes work OK.
As a result, allow escaped symbols to start with a digit.
Add a warning that this syntax is deprecated.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
If VEX.V is an immediate, it should not be subject to register range
checks.
If the WW flag is set, REX_W needs to be OR'd in, not XOR'd, because
the map might have the W bit set for matching purposes.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
- rex2.w is used as a opcode extension (JMPABS), not rex2.x1 as an
earlier version of the spec had.
- Segment prefixes used as Jcc hints are valid in 64-bit mode.
- Avoid duplicate warning messages for ignored/invalid prefixes.
* emit_prefixes() is called twice during code generation.
- Add the UDB #UD opcode in 64-bit mode; SALC is 16/32-bit only.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
Remove the legacy output entry point. It has proven impossible to find
the time to completely port the backends all at once.
Instead, always generate the legacy output data, but put them into the
out_data structure. Then add a macro to explode these arguments into
separate variables, equivalent to the old function arguments. This
also centralizes the type definitions for these variables.
Most importantly, it means that the entire struct out_data is now
always available, which means that backends that need the additional
information available in that structure, such as the specific
instruction template, can access that information without needing to
revamp the entire backend code all at once.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
Add a optimization frameword for operand narrowing (where the operand
size doesn't matter beyond a certain range because only certain bits
are referenced.)
Add a macro *and* matching facility for dealing with segment selectors, which are
typically rm16/r32/r64, but exactly how that is applied varies
depending on if a datum is read or written.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
More work on cleaning up instruction patterns, fixing matchig corner
cases, and tidying up the organization of insns.dat.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
More matching and macrofication work.
Improve some error and warning messages.
Update some travis tests for better messages and added optimizations.
Fix duplicated warning messages for the same out-of-range value
problem.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
Tag pseudo-instructions explicitly and don't set any CPU level flag
for those.
Change insnsa.c to have (length, pointer) rather than using an ever
increasing in size sentinel at the end of each table. This also means
that empty tables (Dx, INCBIN) can be omitted entirely.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Add more instruction macros and fix problems. Adjust some matching
problems.
Remove all FUTURE tags from the instruction list, and add a bunch of
new CPUID tags. Hopefully a small step toward actually getting CPU
feature selection working properly in the future.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
"nw" now means: 64-bit operand size is the default, o32 is not
permitted in 64-bit mode.
"osz" means: instruction size determined by prefixes, otherwise the
mode default.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
This is a WIP checkpoint; not all tests pass yet.
More matching changes, and hopefully something much closer to what
really is desired now. The number of required patterns is now much
smaller.
However, a lot of *changes* are needed to the patterns.
Since some patterns are repeated all over the place, clean up the
x86/addflags.pl script and make it able to generate macro-based
common patterns; first use being the patterns for the "basic 8"
arithmetic patterns.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Work through a number of changes toward making matching a lot saner,
both to reduce the number of patterns to generate for APX but also to
make a number of code patterns simpler.
This replaces a fair number of byte codes.
Improve a number of error messages, especially related to overflows.
Move process_insn() from nasm.c to assemble.c, as it really is the
primary entry point to the assembler module.
Reorder some prefixes. In particular, F2/F3 override 66 when used as a
mandatory prefix, so it makes more sense for them to be closer to the
opcode.
Move a lot more information into struct insn. It is better to have it
in one place; memory consumption is not an issue because struct insn
is transient information.
Get rid of "optimization levels" and replace it with a mask of
flags. That was already halfway done; complete the job.
Replace seg:offset in struct out_data with a struct location. It would
be better to extend this to more places, too.
The ARx and SMx flags are now explicit bitmasks, instead of having a
couple of hard-coded ranges.
Add __func__ to assert or panic messages.
Because of prefix and message changes, a number of travis tests had to
be audited and updated.
Fix a number of instruction patterns which had .128 when they ought to
be .lig. This is no longer a minor issue with the disassembler: for
AVX10, the pattern vector length determines how SAE/RC are encoded,
and there is no valid 128-bit encoding. However, with .lig the 512-bit
encoding can be used.
Separate "o64nw" into two pieces: opsize 64 and "nw" = "REX.w not necessary". The
latter can be included in non-64-bit patterns. "o64" still set REX.W
since that is still the common thing.
New "osz" bytecode: emit an OSP *or* REX.W depending on the current
mode and operand size. Useful for special cases like "nop" where "o64
nop" probably wants to be encoded as "48 90".
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Don't do an out-of-range check for the operands, even
temporarily. Setting the operand pointer to NULL will help catch
errors when accessing non-operands, too.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Merge a bunch of common code in the handling of modr/m
generation. Make the handing of compressed disp8 simpler and more
transparent by exporting a the shift factor for the compressed
immediate in ea_data. For the case of no compression, the shift factor
is simply 0; there is no need to distinguish "compressed" from
"uncompressed".
The tidied up version of the disp8 code is simple enough that it makes
more sense to inline it.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
The {nf} and {zu} prefixes (or suffixes) can be used on a number of
instructions without actually change the encodings (either they don't
touch the flags at all, or they write a 32- or 64-bit register
already.)
Make this a bit more flexible, by adding an FL instruction flag for
the instructions which actually touch the flags, and a ZU instruction
flag for the instructions which zero the upper half.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
EVEX encoding is really messy, with the 4th register bit in one of
several places depending on which type of register it is. It seems to
work now.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
a
Support generating code for APX instruction and add support for the
{nf} prefix.
No disassembler support yet, and only a handful instructions encoded.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
We use this all over the place, so make these general. The sign
extension function existed as signed_bits(), but that is an awfully
confusing name.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
{dfv=} is basically a constant (immediate). Treat it as such during
parsing, except that if "naked" (not in an expression), it has special
matching properties and does not need a terminal comma.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
At least three files (asm/assemble.c, disasm/disasm.c, and
x86/insns.pl) depend on the bytecode defintions. It makes a lot more
sense for them to live in an explicit documentation file in the x86/
directory.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
"LOCK XCHG reg,mem" would issue a warning for being unlockable, which
is incorrect. In this case the RM encoding is simply an alias for the
MR encoding. Add a "LOCK1" bit to deal with that.
However, XCHG is *always* locked, so create a new warning to
explicitly flag a user-specified LOCK XCHG; default off.
Consider optimizing that prefix away in the future, but for now, let's
stick to the user-requested code sequence.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Some target environments may have specific restrictions on what kinds
of relocations are possible or allowed. Allow users to opt-in to
specific warnings as to the relocations they cannot support.
Requested-by: C. Masloch <pushbx@ulukai.org>
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Document CPU LATEVEX and the associated prefixes; add CPU EVEX and CPU
VEX flags to further control encodings.
Fix the error message for invalid encodings due to flags.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
For VEX instructions created *after* the corresponding EVEX
instructions, we need the user to either explicitly declare them {vex}
or specifying "cpu latevex".
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Instead of handling conditional instructions ad hoc, generate
individual instruction patterns as normal. This simplifies the code
and makes CMPccXADD support simpler (otherwise it would be necessary
to hack in the handling of a condition code in the middle of an
instruction.)
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
The FP16 patch had a case of bit overlap. Clean up the handling of
broadcast flags a little in the process.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Add support for AVX512-FP16 instructions and the associated
handling. Allow "mapN" syntax as well as "mN" syntax to match the
documentation.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
