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Commit Graph

5245 Commits

Author SHA1 Message Date
H. Peter Anvin
1284cb15d9 NASM 3.00rc5 nasm-3.00rc5 2025-09-14 04:32:49 -07:00
H. Peter Anvin
31c4d8bcfd doc: describe caveat with old NASM and new %if directives
Older versions of NASM would not try to match unknown %if directives
with a corresponding %endif, resulting in some very odd consequences
when it comes to trying to handle support for multiple NASM versions.

Document the problem.

Reported-by: E. C. Masloch <pushbx@ulukai.org>
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2025-09-14 04:07:19 -07:00
H. Peter Anvin
1f1f3266d6 preproc: look for what looks to be an unknown conditional
If an unknown preprocessor directive starting with %if or %elif is
encountered, assume it should be treated as a conditional directive
for the purpose of balancing %if...%endif.

This avoids some really ugly problems when dealing with code that is
intended to work across NASM versions that uses %if directives that
don't yet exist.

Reported-by: E. C. Masloch <pushbx@ulukai.org>
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-14 03:25:26 -07:00
H. Peter Anvin
f43845f160 stdmac: fix __?NASM_IFDIRECTIVE?__ -> __?NASM_HAS_IFDIRECTIVE?__
The intended form was __?NASM_HAS_IFDIRECTIVE?__, which matches the
documentation but not the code. Fix the code.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-14 02:54:35 -07:00
H. Peter Anvin
7276cfde99 preproc: remove the message-generating functions
The message-generating functions appear to get expanded when they
shouldn't, resulting in errors. Disable them for now and remove them
from the documentation.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-14 02:48:58 -07:00
H. Peter Anvin
84115eeca6 preproc: add %find() and %findi() functions
Add the %find() and %findi() functions to look for a string in a
list. This is useful with picking apart the contents of the
__?DEFAULT?__ macro, for example.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-14 01:24:42 -07:00
H. Peter Anvin
4ccdf7e6fe preproc: add __?DEFAULT?__ macro representing the DEFAULT settings
Create a __?DEFAULT?__ magic macro with the settings of the DEFAULT
directive.

The DEFAULT directive is complex enough that this is best done with a
magic macro.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-14 00:38:50 -07:00
H. Peter Anvin
c719835357 Officially deprecate implicit DEFAULT ABS, add DEFAULT [FS|GS]:[ABS|REL]
Making DEFAULT ABS the default for 64-bit mode was a real
mistake. Issue a warning so we can eventually change it.

Support making FS: and GS: references also be REL by default.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-13 23:15:47 -07:00
H. Peter Anvin
014ca9fdb3 doc: document the %exitmacro directive
The %exitmacro directive was never documented, apparently...

Reported-by: E. C. Masloch <pushbx@ulukai.org>
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2025-09-13 21:47:05 -07:00
H. Peter Anvin
53c2f24c3d doc: 3.0 -> 3.00; tidy up the language for __?NASM_HAS_IFDIRECTIVE?__
Change 3.0 to 3.00 in all version numbers, since NASM has
traditionally expanded all but the major version number to 2 digits.

Make the language related to __?NASM_HAS_IFDIRECTIVE?__ more
consistent.

Reported-by: E. C. Masloch <pushbx@ulukai.org>
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-13 21:35:06 -07:00
H. Peter Anvin
c77549231f NASM 3.00rc4 nasm-3.00rc4 2025-09-13 21:26:13 -07:00
H. Peter Anvin
04c21dc0c5 Allow synthesis of ROLX
If the shift amount is known, there is really no reason why we can't
accept "ROLX" as an alias for "RORX" with a modified shift operand.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-13 21:25:02 -07:00
H. Peter Anvin
01cef66b23 insns.dat/preinsns.pl: fix the RORX, SHLX, SHRX, SARX patterns
These are subtle: RORX is only available in immediate shift count
form, whereas SHLX, SHRX and SARX are only available in register shift
count form...

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-13 20:44:53 -07:00
H. Peter Anvin
9aa48acb3e Merge remote-tracking branch 'yongjie/master' 2025-09-13 20:10:04 -07:00
Yongjie Sheng
87e28e26bd add the remaining missing avx10.1 instructions 2025-09-14 07:15:12 +08:00
Yongjie Sheng
ef4128783f tune VCMPPH instruction and its travis test 2025-09-13 20:28:42 +08:00
Yongjie Sheng
7e304ade60 tune VADDPH instruction and its travis test 2025-09-13 14:23:20 +08:00
Yongjie Sheng
e7a3279828 add avx10_2 instruction VPDPWxxxx family and AVX10_VNNIINT flag 2025-09-13 09:05:56 +08:00
Maciej Wieczor-Retman
3b529c8c62 insns: travis: apx: Add TZCNT instruction
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-12 20:29:36 +02:00
Maciej Wieczor-Retman
f6ad2553ca insns: travis: apx: Add TILELOADD[RS][T1] and TILESTORED instructions
Add database entries and test cases for TILELOADD, TILELOADDT1,
TILELOADDRS, TILELOADDRST1 and TILESTORED.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-12 20:15:50 +02:00
Maciej Wieczor-Retman
3071120a5a travis: apx: Add tests for SUB instruction
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-12 19:30:42 +02:00
Maciej Wieczor-Retman
2497087697 insns: travis: apx: STTILECFG instruction
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-12 19:30:39 +02:00
Maciej Wieczor-Retman
e2d528a938 insns: travis: apx: SHLD and SHRD instructions
Add database entries and test cases for SHLD and SHRD instructions.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-12 15:48:27 +02:00
Maciej Wieczor-Retman
70207aca5a travis: apx: Tests for SBB instruction
Add tests in the arithmetic format for the SBB instruction.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-12 14:42:21 +02:00
Maciej Wieczor-Retman
0f74758bba insns: travis: apx: Shift instructions without affecting flags
Add database entries for SHLX, SARX and SHRX (APX and non-APX). Add
tests to the newly added instructions.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-12 13:29:06 +02:00
Maciej Wieczor-Retman
5b9b5d0280 travis: apx: Tests for SAR/SHL/SHR
Add tests to signed shift instructions that are APX extended.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-12 11:05:12 +02:00
Maciej Wieczor-Retman
bfb26ab467 insns: travis: apx: Implement RORX instruction
Add the RORX instruction to the database - both non-APX and APX
variants.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-11 19:52:54 +02:00
Maciej Wieczor-Retman
fe1c9c380a insns: travis: apx: RDMSR instruction
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-11 19:52:19 +02:00
Maciej Wieczor-Retman
485a09dab6 travis: apx: Test cases for rotate instructions
Tests for RCL, RCR, ROL and ROR.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-11 19:02:10 +02:00
Maciej Wieczor-Retman
2ccd3a93c6 insns: travis: apx: POPCNT instruction
The EGPRs APX case if broken, the non-APX version is used for some
reason.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-11 17:19:31 +02:00
Maciej Wieczor-Retman
7821dd5540 insns: travis: apx: PDEP and PEXT instruction
Add test cases and the database entry for PDEP.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-11 15:56:13 +02:00
Maciej Wieczor-Retman
cbf714d742 travis: apx: OR instruction test cases
Tests similar to other arithmetic instructions.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-11 14:34:40 +02:00
Maciej Wieczor-Retman
55e25b12fe insns: travis: apx: NEG and NOT legacy fix and APX variant
Add test cases and the database entry for the NEG and NOT instructions.

Fix the 0xF7 variants not generating due to a missing hash sign after f6.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-11 14:23:22 +02:00
Maciej Wieczor-Retman
4d0d859dd0 insns: travis: apx: MULX instruction
Add the APX database entry and test cases.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-11 14:17:32 +02:00
Maciej Wieczor-Retman
a3acacc3ad insns: travis: apx: MUL instruction
Add test cases.

Modify what I assume is a typo in the MUL clone of IMUL 0x6B. It should
only use 8bit IMM operand but the preprocessor has i# specified which
would allow other sizes too.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-11 14:17:32 +02:00
Maciej Wieczor-Retman
ed290acf80 insns: travis: apx: APX MOVRS instruction
Add the APX database entry for MOVRS and relevant test cases.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
2025-09-11 14:17:32 +02:00
Yongjie2017
361a1fe4a7 Fix a typo of VGETMANTPH opcode from 25 to 26 per SDM 325462-088 2025-09-10 20:36:00 +08:00
Yongjie2017
967602c195 Fix for VFMSUB132PH instruction family on opcode based on SDM 325462-088 2025-09-10 20:34:06 +08:00
Yongjie2017
396c077d78 Fix for VFMADD132PH instruction family on opcode based on SDM 325462-088 2025-09-10 20:25:17 +08:00
Yongjie2017
d0d802c8f7 Fix a typo of BTR opcode from ab to ba per SDM 325462-088 2025-09-09 22:07:21 +08:00
Yongjie2017
5db0fbe4bd Fix a typo of KSHIFTR opcode base from 32 to 30 per SDM 325462-088 2025-09-09 21:59:15 +08:00
H. Peter Anvin
746fe8384d doc: even more tidying up of text and index
Purely editorial cleanups.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-05 23:59:10 -07:00
H. Peter Anvin
90e37ce7f1 doc: more index tweaks and removal of really really old information
Tidy up the index some more, and remove some very, very out of date
information.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-05 23:36:10 -07:00
H. Peter Anvin
d79fb158e1 outobj: make sure segment alignment warnings are kept
Warnings are flushed at the end of each pass, but the segment
directive in outobj is only processed once. Therefore, keep track of
the originally requested alignment size so the warning can be
re-issued on later passes.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-05 22:10:18 -07:00
H. Peter Anvin
afaa3b5b09 NASM 3.00rc3 nasm-3.00rc3 2025-09-05 20:15:48 -07:00
H. Peter Anvin
fef549da11 zlib: yet one more portability hack
... this time for Win64 ...

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-05 20:08:18 -07:00
H. Peter Anvin
76df52818a zlib: hack for portability...
zlib/zconf.h is ... "special".

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-05 19:59:12 -07:00
H. Peter Anvin
e52aa40daa Include "compiler.h" in zconf.h
This seems to actually work with Z_SOLO? Still might have to resolve
problems, but...

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-05 19:34:34 -07:00
H. Peter Anvin
f129d7ea5b zlib: disable Z_SOLO, enable Z_LARGE64
Without Z_LARGE64, compilation breaks on some platforms. Unfortunately
it seems that Z_SOLO disables Z_LARGE64...

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-05 19:05:35 -07:00
H. Peter Anvin
a3291bd8fb preproc: return NULL, not false
In at least one place, returned false instead of NULL, which caused
build failures on some platforms.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-05 19:04:34 -07:00