Add test cases and the database entry for the NEG and NOT instructions.
Fix the 0xF7 variants not generating due to a missing hash sign after f6.
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
Add test cases.
Modify what I assume is a typo in the MUL clone of IMUL 0x6B. It should
only use 8bit IMM operand but the preprocessor has i# specified which
would allow other sizes too.
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
MOVRS is a pretty basic instruction; it uses the normal operand size
handling.
Fix apx.bin.t accordingly.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
KMOV opcodes of 0x90 and 0x91 have similar bits set in all size
implementations. .66 and .W1 for 32bit, and .NP and .W1 for 64 bits.
Correct my previous mistake where I swapped the VEX/EVEX.pp values by
accident.
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
64bit and 32bit variant of the IMUL 0x6B instruction can't make use of
the zero-upper bit. It gets assembled normally. With equal operand size
this makes sense since 64 and 32 bit legacy behavior was the same as the
APX ZU one. But the 0x6B IMUL variant uses 8 bit immediate values as the
second operand, hence it should be able to make use of ZU for 32 and 64
bit registers too.
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
Some new warnings, some duplicate warnings removed.
The selfref test was broken because of mishandling of $ escaped
symbols; the new set of error messages are far more correct.
With all of this, travis now passes again.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
The crc32 test now does produce the correct output one would expect
for running with optimized assembly.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
Update the apx.bin.t file, since it now produces the same output as it
does with -DSRC and -DBIN.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
Add INVPCI, INVEPT, INVVPID APX instruction variants to the database and
relevant tests.
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
Add the test cases for the IMUL instruction.
Fix the 0x6B database bug that used the same bit width of the immediate
operand as the other operands. Make it 8 bit wide, just like in the
legacy instruction.
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
Clean up CRC32 with $dq macro and add the APX variants.
Also add tests for legacy and APX variants.
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
The ADD, ADC, ADCX, ADOX, AND instruction testcases.
Part of ADCX tests is commented out because addressing with R16-R31 is
currently bugged without some other mechanism indicating using the APX.
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
Add the AOR instruction and use $bwdq macros on the other new atomic
instructions: AADD, AAND and AXOR.
Add tests.
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
This json allows assembling the first column in the testcase macro when
updating the apx.bin.t file, and assembling the second column when
running the test.
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
When throwing one of the "instruction expected" error messages, print
what was encountered instead.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
%unmacro now *is* permitted on a macro being expanded; the entire
expansion is strictly performed when the macro is invoked, and the
lifetime issue related to %unmacro and %exitrep has been hacked
around.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
Add a optimization frameword for operand narrowing (where the operand
size doesn't matter beyond a certain range because only certain bits
are referenced.)
Add a macro *and* matching facility for dealing with segment selectors, which are
typically rm16/r32/r64, but exactly how that is applied varies
depending on if a datum is read or written.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
More matching and macrofication work.
Improve some error and warning messages.
Update some travis tests for better messages and added optimizations.
Fix duplicated warning messages for the same out-of-range value
problem.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
Add more instruction macros and fix problems. Adjust some matching
problems.
Remove all FUTURE tags from the instruction list, and add a bunch of
new CPUID tags. Hopefully a small step toward actually getting CPU
feature selection working properly in the future.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
This is a WIP checkpoint; not all tests pass yet.
More matching changes, and hopefully something much closer to what
really is desired now. The number of required patterns is now much
smaller.
However, a lot of *changes* are needed to the patterns.
Since some patterns are repeated all over the place, clean up the
x86/addflags.pl script and make it able to generate macro-based
common patterns; first use being the patterns for the "basic 8"
arithmetic patterns.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Work through a number of changes toward making matching a lot saner,
both to reduce the number of patterns to generate for APX but also to
make a number of code patterns simpler.
This replaces a fair number of byte codes.
Improve a number of error messages, especially related to overflows.
Move process_insn() from nasm.c to assemble.c, as it really is the
primary entry point to the assembler module.
Reorder some prefixes. In particular, F2/F3 override 66 when used as a
mandatory prefix, so it makes more sense for them to be closer to the
opcode.
Move a lot more information into struct insn. It is better to have it
in one place; memory consumption is not an issue because struct insn
is transient information.
Get rid of "optimization levels" and replace it with a mask of
flags. That was already halfway done; complete the job.
Replace seg:offset in struct out_data with a struct location. It would
be better to extend this to more places, too.
The ARx and SMx flags are now explicit bitmasks, instead of having a
couple of hard-coded ranges.
Add __func__ to assert or panic messages.
Because of prefix and message changes, a number of travis tests had to
be audited and updated.
Fix a number of instruction patterns which had .128 when they ought to
be .lig. This is no longer a minor issue with the disassembler: for
AVX10, the pattern vector length determines how SAE/RC are encoded,
and there is no valid 128-bit encoding. However, with .lig the 512-bit
encoding can be used.
Separate "o64nw" into two pieces: opsize 64 and "nw" = "REX.w not necessary". The
latter can be included in non-64-bit patterns. "o64" still set REX.W
since that is still the common thing.
New "osz" bytecode: emit an OSP *or* REX.W depending on the current
mode and operand size. Useful for special cases like "nop" where "o64
nop" probably wants to be encoded as "48 90".
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Merge a bunch of common code in the handling of modr/m
generation. Make the handing of compressed disp8 simpler and more
transparent by exporting a the shift factor for the compressed
immediate in ea_data. For the case of no compression, the shift factor
is simply 0; there is no need to distinguish "compressed" from
"uncompressed".
The tidied up version of the disp8 code is simple enough that it makes
more sense to inline it.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
EVEX encoding is really messy, with the 4th register bit in one of
several places depending on which type of register it is. It seems to
work now.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Clean up the handling of prefixes in general. Allow a set of braced
prefixes to follow the instruction; this is required for things like
{dfv=} but might also be a nicer syntax for things like {rex}.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Nothing wrong, but the text of the warning message has changed after
subordinating it to another warning.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
NASM would try to "eat the comma token" in db expressions, even for
cases where the token was not a comma. Fix that and error out
properly.
To give better error messages, track where in the input string a token
starts or ends. This information is only valid as long as the input
string is kept, but that is just fine for error messages during
parsing.
Reported-by: Peter Cordes <pcordes@gmail.com>
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
