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Commit Graph

323 Commits

Author SHA1 Message Date
H. Peter Anvin (Intel)
ae9335a0b9 labels: make the prefix/suffix options and pragmas consistent
Make the spellings for the label-mangling options and pragmas
consistent, and implement the directive forms which were documented
but never implemented.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-10-07 18:46:39 -07:00
Yongjie Sheng
9cb23294a4 fix a displacement offset calculation error for movddup 2025-10-07 14:35:45 +08:00
H. Peter Anvin
f6a17a29c0 nasmlib.h: protect list_last() macro against misuse
The list_last() macro is a statement macro; wrap it in a
do { ... } while(0) block to prevent accidental misuse.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-10-06 14:27:30 -07:00
Adam Sampson
a65be7d59b bytesex.h: fix typo in le32toh function name
This fixes the build on 32-bit/64-bit ARM.

Signed-off-by: Adam Sampson <ats@offog.org>
2025-10-04 15:54:49 -07:00
H. Peter Anvin
b4697f09e7 Conditionalize __builtin_prefetch() on it existing!!
You have to check that something that isn't standard C actually exists
before trying to use it...

Cc: Colin Ian King <colin.i.king@intel.com>
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-10-03 10:47:23 -07:00
H. Peter Anvin
0b3c971f5b portability: "const macros_t" is redundant
Some C compilers don't like that...

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-10-01 13:55:38 -07:00
H. Peter Anvin
23ce05f906 treewide: replace verbose copyright headers with SPDX tags
SPDX is an international standard for documenting software license
requirements. Remove the existing headers and replace with a brief
SPDX preamble.

See: https://spdx.dev/use/specifications/

The script used to convert the files is added to "tools", and the
file header templates in headers/ are updated.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-10-01 11:45:31 -07:00
H. Peter Anvin
595afc6f4b portability: add missing PRI* constants, signed 1 in bitfield hack
Add missing uses of PRI constants.

Create a PRI constant for size_t, since %z isn't available on all
platforms. Notably, the legacy Windows runtime needs %I instead of %z.
Use that on UCRT as well, since there doesn't seem to be a way to
determine if you are compiling for MSVCRT or UCRT.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-30 09:41:03 -07:00
H. Peter Anvin
df6b966ca9 nasmlib.h: use int for the enum macros, for strict ISO C
ISO C before C23 restricted enum ranges to type "int" (not even
"unsigned int"). This limits the usability of enums for bit fields,
but it still covers our main use cases.

On gcc/clang this just produces a warning, but who knows what other
compilers will do.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-25 08:33:17 -07:00
H. Peter Anvin
c4ed07830a Tidy up the morass of EVEX bitfield constants
The EVEX bitfields are complicated at best. Tidy them up to the
best of our ability.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-20 18:26:27 -07:00
H. Peter Anvin
47c56d122e nasmlib: set of neat macros to create a useful bitfield enum
When dealing with bitmasks/bitfields, definining them in macros tends
to cause a lot of desirable constants out because it is a pain to
create all of them.  C macros can't create other macros, but they
*can* be used to create fields in an enum, so provide some neat
convenience macros for doing so.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-20 18:25:32 -07:00
H. Peter Anvin
861782dc88 compiler.h: has_attribute() is broken on some gcc versions
Apparently the has_attribute() macro triggers false positives on at
least gcc 5.3, which is the version that the build server uses with
djgpp.

Drop using it, so much for trying to be standards-compliant...

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-16 15:27:34 -07:00
H. Peter Anvin
55dd65cddc portability: speed and modernize autoconf; compiler.h improvements
- Add some features to autoconf that makes it cleaner and faster
- Modernize some of the autoconf macros
- Update compiler.h with some C23 features

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-16 13:25:39 -07:00
H. Peter Anvin
f6166e571a preproc: implement %hs2b() and %b2hs() functions for compact binary data
Convenience preprocessor functions that allows for efficient packing
of binary data in source code.

Move some functions that has previously been local but are more
generally useful into more accessible places.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-15 23:01:59 -07:00
H. Peter Anvin
dc247c9f99 Speed up autoconf, use POSIX names instead of cpu_to_le*()
The POSIX names for these functions are htole*(). Use those
preferentially.

Speed up autoconf by allowing early-out during alternative function
searches.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-15 18:26:25 -07:00
H. Peter Anvin
c719835357 Officially deprecate implicit DEFAULT ABS, add DEFAULT [FS|GS]:[ABS|REL]
Making DEFAULT ABS the default for 64-bit mode was a real
mistake. Issue a warning so we can eventually change it.

Support making FS: and GS: references also be REL by default.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-13 23:15:47 -07:00
H. Peter Anvin
04c21dc0c5 Allow synthesis of ROLX
If the shift amount is known, there is really no reason why we can't
accept "ROLX" as an alias for "RORX" with a modified shift operand.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-13 21:25:02 -07:00
H. Peter Anvin
ac93d75da3 Sanitize the handling of messsages; improve info and debug
Make the handling of messages saner. In particular, regularize the
handling of info and debug messages, so that nasm_info() and
nasm_debug() actually become useful.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-05 12:53:20 -07:00
H. Peter Anvin
31a160759d Add %ifdirective preprocessor directive
Along with C and other languages, the current trend is to be able to
probe for features rather than relying on version numbers. This is
motivated in part by the intent of bumping the major version number to
3.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-04 19:41:12 -07:00
H. Peter Anvin
61b525fbc1 nasmlib.h: add convenience macros for iterating over fixed arrays
Iterating over fixed arrays is a common operation; add macros to
simplify the task.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-04 17:09:57 -07:00
H. Peter Anvin
178a1b7443 Add directive to disable dollar-hex constants
The use of $ prefixes for hexadecimal numbers conflicts with
the use of $ to escape symbols.  Add a directive to disable
$ for hexadecimal numbers so that those escapes work OK.

As a result, allow escaped symbols to start with a digit.

Add a warning that this syntax is deprecated.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-03 00:35:41 -07:00
H. Peter Anvin
80225b4722 Add support for the {pt} and {pn} branch hint prefixes
Add support for the {pt} and {pn} branch hint prefixes, now when they
are no longer orphanned...

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-02 16:29:46 -07:00
H. Peter Anvin
acd01496d7 asm: distinguish between VEX.V as an immediate and a prefix; fix WW
If VEX.V is an immediate, it should not be subject to register range
checks.

If the WW flag is set, REX_W needs to be OR'd in, not XOR'd, because
the map might have the W bit set for matching purposes.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-02 15:38:49 -07:00
H. Peter Anvin
e05867ce3d ndisasm: make the assembler (hopefully) work again
- Significantly overhauled the disassembler internals to make
  better use of the information already in the instruction template
  and to reduce the implementation differences with the assembler
- Add APX support to the disassembler
- Fix problem with disassembler truncating addresses of jumps
- Fix generation of invalid EAs in 16-bit mode
- Fix array overrun for types in a few modules
- Fix invalid ND flag on near JMP

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-08-30 16:16:43 -07:00
H. Peter Anvin
9f86275c74 Merge remote-tracking branch 'origin/master' into apx.wip
Resolved Conflicts:
	disasm/disasm.c

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-08-29 01:51:27 -07:00
H. Peter Anvin
7a5502142b bytesex, ilog2: use C23 <stdbit.h> if available; use in disassembler
Merge the macros used in the assembler and disassembler.
Simplify and slightly correct the byte order/unaligned handling macros.
Use <stdbit.h> from C23 if available for bytesex.h and ilog2.h.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-08-29 01:46:57 -07:00
H. Peter Anvin
83534f1f37 Merge remote-tracking branch 'origin/master' into apx.wip
Resolved Conflicts:
	Makefile.in
	Mkfiles/msvc.mak
	Mkfiles/openwcom.mak
	asm/assemble.c
	asm/nasm.c
	asm/parser.c
	doc/Makefile.in
	include/nasm.h
	include/tables.h
	output/legacy.c
	travis/test/br3392531.stderr
	travis/test/br3392716.stderr
	travis/test/org.stderr
	x86/insns.dat

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-08-25 21:09:15 -07:00
H. Peter Anvin
0b73367874 nasmlib/asprintf: check the return value from vsnprintf()
Without this, gcc may throw a warning which breaks the --enable-werror
build. It is good practice anyway...

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-08-25 20:10:41 -07:00
H. Peter Anvin
df4555d68b preproc: compress standard macros with zlib
The very simple compression scheme used for the builtin macro sets no
longer works adequately, and in fact it generates incorrect output
now.

Drop the whole idea of an ad hoc compression scheme and just use
zlib. For the case where there is no system zlib available, include a
(subset of) the zlib distribution. The configure script can be set to
force this included zlib if desired (e.g. for testing.)

Unfortunately this turned out to be a pretty painful can of worms in
terms of complexity. On the other hand having zlib available might be
useful at some point in the future.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-08-15 16:51:39 -07:00
H. Peter Anvin
2726aefb06 output: remove the legacy output entry point
Remove the legacy output entry point. It has proven impossible to find
the time to completely port the backends all at once.

Instead, always generate the legacy output data, but put them into the
out_data structure. Then add a macro to explode these arguments into
separate variables, equivalent to the old function arguments. This
also centralizes the type definitions for these variables.

Most importantly, it means that the entire struct out_data is now
always available, which means that backends that need the additional
information available in that structure, such as the specific
instruction template, can access that information without needing to
revamp the entire backend code all at once.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-08-13 13:51:25 -07:00
H. Peter Anvin
ef5fd5391c error.h: add prototypes for nasm_note[f]()
Apparently -Wall -W doesn't enable -Wmissing-prototypes for some
bizarre reason.

This allowed this to slink through unnoticed.

Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2024-11-04 10:17:06 -08:00
H. Peter Anvin
8d62e99e14 Add %note directive to add a note in the list file
This differs from a plain old comment in the following ways:

1. It is optionally macro-expanded;
2. It has a dash prefix;
3. It can be used inside .nolist macros.

Suggested-by: <pushbx@ulukai.org>
Resolves: https://bugzilla.nasm.us/show_bug.cgi?id=3392915
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2024-09-19 13:21:30 +02:00
H. Peter Anvin
49a56ea9ee Add optimization for operand narrowing; tidy up selector handling
Add a optimization frameword for operand narrowing (where the operand
size doesn't matter beyond a certain range because only certain bits
are referenced.)

Add a macro *and* matching facility for dealing with segment selectors, which are
typically rm16/r32/r64, but exactly how that is applied varies
depending on if a datum is read or written.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2024-08-23 02:25:21 -07:00
H. Peter Anvin
253ff4f370 insns: tag pseudo-instructions explicitly; change insnsa.c format
Tag pseudo-instructions explicitly and don't set any CPU level flag
for those.

Change insnsa.c to have (length, pointer) rather than using an ever
increasing in size sentinel at the end of each table. This also means
that empty tables (Dx, INCBIN) can be omitted entirely.

Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2024-08-21 12:50:31 -07:00
H. Peter Anvin
58024b4611 insns: more instruction macroizing/fixups; remote FUTURE tags
Add more instruction macros and fix problems. Adjust some matching
problems.

Remove all FUTURE tags from the instruction list, and add a bunch of
new CPUID tags. Hopefully a small step toward actually getting CPU
feature selection working properly in the future.

Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2024-08-21 11:48:47 -07:00
H. Peter Anvin
75f6f4cdb2 WIP: more matching and template work
Further work on a better matching system. Still a work in progress,
however.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2024-08-20 12:59:07 -07:00
H. Peter Anvin
f114a6276e insns: more macroization and organization
Macroize and update more instruction patterns.

Begin organizing the instructions by functional groups.

Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2024-08-15 22:15:48 -07:00
H. Peter Anvin
05f1b6b658 insns: sanitize the handling of "nw" and "osz"; fix more patterns
"nw" now means: 64-bit operand size is the default, o32 is not
permitted in 64-bit mode.

"osz" means: instruction size determined by prefixes, otherwise the
mode default.

Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2024-08-15 17:52:54 -07:00
H. Peter Anvin
557d99d796 insns: more macro goodness
Even better macro support, add match for the BX register.

Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2024-08-14 20:48:18 -07:00
H. Peter Anvin
c9457d42a6 WIP checkpoint: more matching changes, starting to work on patterns
This is a WIP checkpoint; not all tests pass yet.

More matching changes, and hopefully something much closer to what
really is desired now. The number of required patterns is now much
smaller.

However, a lot of *changes* are needed to the patterns.

Since some patterns are repeated all over the place, clean up the
x86/addflags.pl script and make it able to generate macro-based
common patterns; first use being the patterns for the "basic 8"
arithmetic patterns.

Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2024-08-11 21:28:57 -07:00
H. Peter Anvin
7c47273c45 struct insn: remove unused forw_ref flag
The forw_ref flag in struct insn was being set but never actually read
anywhere.

Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2024-08-10 15:01:43 -07:00
H. Peter Anvin
bff94fbd39 Major changes to a number of subsystems to improve matching
Work through a number of changes toward making matching a lot saner,
both to reduce the number of patterns to generate for APX but also to
make a number of code patterns simpler.

This replaces a fair number of byte codes.

Improve a number of error messages, especially related to overflows.

Move process_insn() from nasm.c to assemble.c, as it really is the
primary entry point to the assembler module.

Reorder some prefixes. In particular, F2/F3 override 66 when used as a
mandatory prefix, so it makes more sense for them to be closer to the
opcode.

Move a lot more information into struct insn. It is better to have it
in one place; memory consumption is not an issue because struct insn
is transient information.

Get rid of "optimization levels" and replace it with a mask of
flags. That was already halfway done; complete the job.

Replace seg:offset in struct out_data with a struct location. It would
be better to extend this to more places, too.

The ARx and SMx flags are now explicit bitmasks, instead of having a
couple of hard-coded ranges.

Add __func__ to assert or panic messages.

Because of prefix and message changes, a number of travis tests had to
be audited and updated.

Fix a number of instruction patterns which had .128 when they ought to
be .lig. This is no longer a minor issue with the disassembler: for
AVX10, the pattern vector length determines how SAE/RC are encoded,
and there is no valid 128-bit encoding. However, with .lig the 512-bit
encoding can be used.

Separate "o64nw" into two pieces: opsize 64 and "nw" = "REX.w not necessary". The
latter can be included in non-64-bit patterns. "o64" still set REX.W
since that is still the common thing.

New "osz" bytecode: emit an OSP *or* REX.W depending on the current
mode and operand size. Useful for special cases like "nop" where "o64
nop" probably wants to be encoded as "48 90".

Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2024-08-07 17:13:44 -07:00
H. Peter Anvin
7eb0045c5d Merge remote-tracking branch 'origin/master' into apx.wip
Resolved Conflicts:
	asm/assemble.c
	asm/parser.c
	include/nasm.h

Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2024-08-04 23:55:42 -07:00
H. Peter Anvin
86142b00e1 assemble: limit-check operand references
Don't do an out-of-range check for the operands, even
temporarily. Setting the operand pointer to NULL will help catch
errors when accessing non-operands, too.

Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2024-08-04 23:45:20 -07:00
H. Peter Anvin
de84c3dcc0 insns.h: update the prototype for the disassembly root table
The disassembly table is now totally different, so update the header
file accordingly.

Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2024-08-04 16:13:14 -07:00
H. Peter Anvin
5225d57cd7 Correctly handle instruction masking based on {zu} flag
Fix instruction masking based on {zu} flag.

Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2024-08-03 18:54:13 -07:00
H. Peter Anvin
1286a2da4e Tidy up handling of modr/m and compressed immediates
Merge a bunch of common code in the handling of modr/m
generation. Make the handing of compressed disp8 simpler and more
transparent by exporting a the shift factor for the compressed
immediate in ea_data. For the case of no compression, the shift factor
is simply 0; there is no need to distinguish "compressed" from
"uncompressed".

The tidied up version of the disp8 code is simple enough that it makes
more sense to inline it.

Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2024-08-03 16:24:49 -07:00
H. Peter Anvin
b5e613fdf8 Allow more flexiblity for {nf} and {zu}
The {nf} and {zu} prefixes (or suffixes) can be used on a number of
instructions without actually change the encodings (either they don't
touch the flags at all, or they write a 32- or 64-bit register
already.)

Make this a bit more flexible, by adding an FL instruction flag for
the instructions which actually touch the flags, and a ZU instruction
flag for the instructions which zero the upper half.

Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2024-07-31 17:23:06 -07:00
H. Peter Anvin
dda9152b35 apx: smarter determination of REX2 prefix eligibility
REX2 encoding is mostly default, so flag the instruction patters which
do *not* support REX2 instead.

Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2024-07-31 16:18:17 -07:00
H. Peter Anvin
fd08822070 apx: implement JMPABS
Implement the JMPABS instruction, which can also be specified as JMP
ABS for consistency. Since ABS is already a keyword, this does not
pollute the namespace.

Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2024-07-30 17:32:00 -07:00