Add instructions for Intel Control Flow Enforcement Technology (CET).
Signed-off-by: Henrik Gramner <henrik@gramner.com>
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
The a64 instruction patterns would incorrectly force REX to zero at a
point where REX prefixes have already been assigned. This is not only
incorrect in case of instructions which can use high registers, but it
causes an assertion failure. It happened to work for J*CXZ and LOOP*.
Reported-by: Philip Lantz <philip.lantz@intel.com>
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
When using VCMP and VPCMP operations with the condition in the opcode,
we should not have an immediate operand!
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
CMPXCHG8b/16b should be legitimate with an explicit operand size.
Reported-by: Xusheng Li <xushengli@protonmail.com>
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
We need the instruction table to contain the correct information for
both the reg and the rm field in the various modes.
Reported-by: <fasdfqwer@mail.com>
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
The two VPSH{R|L}DV* instructions had the wrong opcode.
Reported-by: Henrik Gramner <herik@gramner.com>
Link: https://bugzilla.nasm.us/show_bug.cgi?id=3392607
Signed-off-by: Henrik Gramner <henrik@gramner.com>
Signed-off-by: Chang S. Bae <chang.seok.bae@intel.com>
The memory operand size of LEA doesn't matter in any way as it isn't
"real memory". Add an ANYSIZE option to ignore sizes entirely.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
Distinguish instructions which have once been valid (OBSOLETE) from
those that never saw the light of day (NEVER). Futhermore, flag
instructions which devolve to an architectural noop from those with
undefined behavior and possibly recycled opcodes.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
This allows the K instructions to be specified without a size suffix
as long as the operands are sized; this matches the way most other x86
instructions work. As this is not the syntax specified in the SDM,
don't use it for disassembly.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
AMD documents this instruction with an rax operand. The error behavior
implies this is an address-size-sensitive instruction. Add support for
specifying the explicit operand, but consistent with normal ndisasm
behavior, don't disassemble the implicit operand.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Support the +n syntax for multiple contiguous registers, and emit it
in the output from ndisasm as well.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
New instructions which do four full iterations of a data-reduction
operation (FMA, dot product.)
Bug report: https://bugzilla.nasm.us/show_bug.cgi?id=3392492
Reported-by: ff_ff <qqqqqqqqqfffffffff@gmail.com>
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
Add PTWRITE instruction. It is worth noting that we should
be able to do "ptwrite [eax]" in 32-bit mode, but the instruction
selector doesn't currently handle that well in a way that doesn't make
64-bit mode very confusing.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
Add instructions from the Intel Instruction Set Extensions and Future
Features Programming Reference, document 319433-034, May 2018.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Make it possible to generate variants of RET(F) with explicit operand
size specified without having to use o16/o32/o64.
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
We could generate the MRI version (SSE 4.1) instead of the RMI
(SSE 2) version of these instructions if a 64-bit register was given
as the destination.
Reported-by: Vasiliy Olekhov <olekhov@gmail.com>
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
We don't need to sort opcodes anymore, since we are using an O(1) hash
and not binary search. Instead, sort them in the order they first
appear in insns.dat; this lets us move all the pseudo-ops to a
contiguous range at the start of the file, for more efficient
handling.
Change the functions that process pseudo-ops accordingly.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Compactify the instruction list in the documentation to have fewer
margin violations, and fix some of the headings (;#).
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
The fvm: annotation to generate the correct EVEX compressed
displacements had inadvertently gotten dropped from a handful of
instructions in checkin c33d95fde9f8ae6252c8ecf4d66c543dfa914d83:
BR 3392370: {z} decorator allowed on MOVDQ* memory operands
Put them back, and verify they work.
Reported-by: Henrik <henrik@gramner.com>
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
insns-iflags.ph is included from another Perl script, so rename it .ph
(Perl header). Add missing dependency to the main Makefile.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
The spec says very clearly the {z} decorator is allowed on memory
operands for the MOVDQ* instructions. Remove special cases from the
code to disallow this case, which had the unfortunate effect of
generating a very uninformative error message.
Reported-by: Agner <agner@agner.org>
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
The UD0 and UD1 opcodes are now officially documented, with UD1
officially documented to take a modr/m. Still permit the "UD2B" and
argument-less aliases, but not as preferred.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
In commit 1eef781594b08a7f we allowed xmm0
to be implicit, then in dcaef4b09502aae7 it
occasionally got ripped off. Move it back.
https://bugzilla.nasm.us/show_bug.cgi?id=3392379
Reported-by: ig <glucksmann@avast.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Improve consistency by allowing contracted forms for EVEX-encoded
instructions when it's allowed for similar VEX-encoded instructions.
Previously the behavior would change depending on the vector size or
the register number which could be somewhat confusing:
vaddps xmm0, xmm1 ; ok
vaddps ymm0, ymm1 ; ok
vaddps zmm0, zmm1 ; error
vaddps xmm0, xmm16 ; error
Also allow contracted forms for a few additional older AVX instructions
where it makes sense.
Signed-off-by: Henrik Gramner <henrik@gramner.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Make the source code easier to understand and keep track of by
organizing it into subdirectories depending on the function.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
