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mirror of https://github.com/netwide-assembler/nasm.git synced 2025-07-24 10:25:42 -04:00

5 Commits

Author SHA1 Message Date
H. Peter Anvin
3b55b62f02 apx: implement the mechanism for evex.zu
Implement the mechanism needed to handle {zu} suffixes that actually
set ND (IMUL, SETcc).

Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2024-08-14 15:44:38 -07:00
H. Peter Anvin
bff94fbd39 Major changes to a number of subsystems to improve matching
Work through a number of changes toward making matching a lot saner,
both to reduce the number of patterns to generate for APX but also to
make a number of code patterns simpler.

This replaces a fair number of byte codes.

Improve a number of error messages, especially related to overflows.

Move process_insn() from nasm.c to assemble.c, as it really is the
primary entry point to the assembler module.

Reorder some prefixes. In particular, F2/F3 override 66 when used as a
mandatory prefix, so it makes more sense for them to be closer to the
opcode.

Move a lot more information into struct insn. It is better to have it
in one place; memory consumption is not an issue because struct insn
is transient information.

Get rid of "optimization levels" and replace it with a mask of
flags. That was already halfway done; complete the job.

Replace seg:offset in struct out_data with a struct location. It would
be better to extend this to more places, too.

The ARx and SMx flags are now explicit bitmasks, instead of having a
couple of hard-coded ranges.

Add __func__ to assert or panic messages.

Because of prefix and message changes, a number of travis tests had to
be audited and updated.

Fix a number of instruction patterns which had .128 when they ought to
be .lig. This is no longer a minor issue with the disassembler: for
AVX10, the pattern vector length determines how SAE/RC are encoded,
and there is no valid 128-bit encoding. However, with .lig the 512-bit
encoding can be used.

Separate "o64nw" into two pieces: opsize 64 and "nw" = "REX.w not necessary". The
latter can be included in non-64-bit patterns. "o64" still set REX.W
since that is still the common thing.

New "osz" bytecode: emit an OSP *or* REX.W depending on the current
mode and operand size. Useful for special cases like "nop" where "o64
nop" probably wants to be encoded as "48 90".

Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2024-08-07 17:13:44 -07:00
H. Peter Anvin
5225d57cd7 Correctly handle instruction masking based on {zu} flag
Fix instruction masking based on {zu} flag.

Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2024-08-03 18:54:13 -07:00
H. Peter Anvin
dda9152b35 apx: smarter determination of REX2 prefix eligibility
REX2 encoding is mostly default, so flag the instruction patters which
do *not* support REX2 instead.

Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2024-07-31 16:18:17 -07:00
H. Peter Anvin
2e4df506e0 WIP: APX: can now generate code for tested APX instructions
a
Support generating code for APX instruction and add support for the
{nf} prefix.

No disassembler support yet, and only a handful instructions encoded.

Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2024-07-29 20:58:04 -07:00