2 Commits

Author	SHA1	Message	Date
H. Peter Anvin	973fe19a1b	WIP: apx: now can encode most instructions; handle subcases in EVEX ... EVEX encoding is really messy, with the 4th register bit in one of several places depending on which type of register it is. It seems to work now. Signed-off-by: H. Peter Anvin <hpa@zytor.com>	2024-07-30 17:03:58 -07:00
H. Peter Anvin (Intel)	d85a6101d7	BR 3392681: handle a64 instruction patters correctly ... The a64 instruction patterns would incorrectly force REX to zero at a point where REX prefixes have already been assigned. This is not only incorrect in case of instructions which can use high registers, but it causes an assertion failure. It happened to work for J*CXZ and LOOP*. Reported-by: Philip Lantz <philip.lantz@intel.com> Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>	2020-06-22 13:52:02 -07:00