aniani/nasm
0
0
Fork 1
mirror of https://github.com/netwide-assembler/nasm.git synced 2025-09-22 10:43:39 -04:00
Code Activity

x86: sync updated instructions from the master branch

Browse Source 
Sync updated instructions from the master branch as of 2022-11-06.

Signed-off-by: H. Peter Anvin <hpa@zytor.com>
This commit is contained in:
H. Peter Anvin
2022-11-07 09:44:16 -08:00
parent b6151260a1
commit eebdba7d55
2 changed files with 17 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
x86/iflags.ph
View File

@@ -95,6 +95,7 @@ if_("AVX512VP2INTERSECT", "AVX-512 VP2INTERSECT instructions");
if_("AMXTILE", "AMX tile configuration instructions"); if_("AMXTILE", "AMX tile configuration instructions");
if_("AMXBF16", "AMX bfloat16 multiplication"); if_("AMXBF16", "AMX bfloat16 multiplication");
if_("AMXINT8", "AMX 8-bit integer multiplication"); if_("AMXINT8", "AMX 8-bit integer multiplication");
if_("FRED", "Flexible Return and Exception Delivery (FRED)");
# Put these last [hpa: why?] # Put these last [hpa: why?]
if_("OBSOLETE", "Instruction removed from architecture"); if_("OBSOLETE", "Instruction removed from architecture");

18
x86/insns.dat
View File

@@ -715,8 +715,9 @@ JMP rm64 [m: o64nw ff /4] X86_64,LONG,BND
JMPE imm [i: odf 0f b8 rel] IA64 JMPE imm [i: odf 0f b8 rel] IA64
JMPE imm16 [i: o16 0f b8 rel] IA64 JMPE imm16 [i: o16 0f b8 rel] IA64
JMPE imm32 [i: o32 0f b8 rel] IA64 JMPE imm32 [i: o32 0f b8 rel] IA64
JMPE rm16 [m: o16 0f 00 /6] IA64 JMPE rm16 [m: norep o16 0f 00 /6] IA64
JMPE rm32 [m: o32 0f 00 /6] IA64 JMPE rm32 [m: norep o32 0f 00 /6] IA64
JMPE rm64 [m: norep o64 0f 00 /6] IA64,LONG
LAHF void [ 9f] 8086 LAHF void [ 9f] 8086
LAR reg16,mem [rm: o16 0f 02 /r] 286,PROT,SW LAR reg16,mem [rm: o16 0f 02 /r] 286,PROT,SW
LAR reg16,reg16 [rm: o16 0f 02 /r] 286,PROT LAR reg16,reg16 [rm: o16 0f 02 /r] 286,PROT
@@ -1900,6 +1901,11 @@ INVEPT reg32,mem [rm: 66 0f 38 80 /r] VMX,SO,NOLONG
INVEPT reg64,mem [rm: o64nw 66 0f 38 80 /r] VMX,SO,LONG INVEPT reg64,mem [rm: o64nw 66 0f 38 80 /r] VMX,SO,LONG
INVVPID reg32,mem [rm: 66 0f 38 81 /r] VMX,SO,NOLONG INVVPID reg32,mem [rm: 66 0f 38 81 /r] VMX,SO,NOLONG
INVVPID reg64,mem [rm: o64nw 66 0f 38 81 /r] VMX,SO,LONG INVVPID reg64,mem [rm: o64nw 66 0f 38 81 /r] VMX,SO,LONG
;# SEV-SNP AMD instructions
PVALIDATE void [ f2 0f 01 ff] VMX,AMD
RMPADJUST void [ f3 0f 01 fe] VMX,AMD
VMGEXIT void [ f2 0f 01 c1] VMX,AMD
VMGEXIT void [ f3 0f 01 c1] VMX,AMD
;# Tejas New Instructions (SSSE3) ;# Tejas New Instructions (SSSE3)
PABSB mmxreg,mmxrm [rm: np 0f 38 1c /r] SSSE3,MMX,SQ PABSB mmxreg,mmxrm [rm: np 0f 38 1c /r] SSSE3,MMX,SQ
@@ -6055,6 +6061,14 @@ TILERELEASE void [ vex.128.np.0f38.w0 49 c0] AMXTILE,FUTURE,LONG
TILESTORED mem,tmmreg [mr: vex.128.f3.0f38.w0 4b /r] AMXTILE,MIB,SIB,FUTURE,SX,LONG TILESTORED mem,tmmreg [mr: vex.128.f3.0f38.w0 4b /r] AMXTILE,MIB,SIB,FUTURE,SX,LONG
TILEZERO tmmreg [r: vex.128.f2.0f38.w0 49 /3r0] AMXTILE,FUTURE,LONG TILEZERO tmmreg [r: vex.128.f2.0f38.w0 49 /3r0] AMXTILE,FUTURE,LONG
;# Flexible Return and Exception Delivery (FRED)
ERETS void [ f2 0f 01 ca] FRED,FUTURE,LONG,PRIV
ERETU void [ f3 0f 01 ca] FRED,FUTURE,LONG,PRIV
LKGS reg16 [m: f2 0f 00 /6] FRED,FUTURE,LONG,PRIV
LKGS reg32 [m: f2 0f 00 /6] FRED,FUTURE,LONG,PRIV,ND
LKGS reg64 [m: f2 0f 00 /6] FRED,FUTURE,LONG,PRIV,ND
LKGS mem [m: f2 0f 00 /6] FRED,FUTURE,LONG,PRIV,SW
;# Systematic names for the hinting nop instructions ;# Systematic names for the hinting nop instructions
; These should be last in the file ; These should be last in the file
HINT_NOP0 rm16 [m: o16 0f 18 /0] P6,UNDOC HINT_NOP0 rm16 [m: o16 0f 18 /0] P6,UNDOC