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insns: fix MOVBE CPUID flag, BSWAP 16-bit XCHG patterns

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Add the MOVBE CPUID flag, add helper patterns for 16-bit BSWAP
emulation. Unfortunately using ROL/ROR for registers other than the
ones for which XCHG can work clobbers the flags.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
This commit is contained in:
H. Peter Anvin 2024-08-22 23:32:42 -07:00
parent 2b2f1fc98a
commit ecbd1c81b3
2 changed files with 13 additions and 9 deletions
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8
x86/iflags.ph
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@ -161,9 +161,11 @@ if_("MONITORX", "MONITORX and MWAITX");
if_("WAITPKG", "User wait instruction package"); if_("WAITPKG", "User wait instruction package");
# Single-instruction CPUID bits without additional help text # Single-instruction CPUID bits without additional help text
foreach my $ins (qw(invpcid prefetchwt1 pconfig wbnoinvd serialize lkgs my @oneins = qw(invpcid prefetchwt1 pconfig wbnoinvd serialize lkgs
wrmsrns clflushopt clwb rdrand rdseed rdpid wrmsrns clflushopt clwb rdrand rdseed rdpid
lzcnt ptwrite cldemote movdiri movdir64b clzero)) { lzcnt ptwrite cldemote movdiri movdir64b clzero
movbe);
foreach my $ins (@oneins) {
if_($ins, "\U$ins\E instruction"); if_($ins, "\U$ins\E instruction");
} }

14
x86/insns.dat
View File

@ -192,12 +192,14 @@ AAS void [ 3f] 8086,NOLONG
DAA void [ 27] 8086,NOLONG DAA void [ 27] 8086,NOLONG
DAS void [ 2f] 8086,NOLONG DAS void [ 2f] 8086,NOLONG
; --- ;# Endianness handling
$dq BSWAP reg# [r: o# 0f c8+r] 486
;# Endianness instructions BSWAP reg_ax [-: 86 c4] 8086,OPT,ND
$wdq BSWAP reg# [r: o# 0f c8+r] 486,(w:UNDOC) BSWAP reg_cx [-: 86 cd] 8086,OPT,ND
$wdq MOVBE reg#,mem# [rm: o# norep 0f38 f0 /r] NEHALEM,SM BSWAP reg_dx [-: 86 d6] 8086,OPT,ND
$wdq MOVBE mem#,reg# [mr: o# norep 0f38 f1 /r] NEHALEM,SM BSWAP reg_bx [-: 86 df] 8086,OPT,ND
$wdq MOVBE reg#,mem# [rm: o# norep 0f38 f0 /r] NEHALEM,MOVBE,SM
$wdq MOVBE mem#,reg# [mr: o# norep 0f38 f1 /r] NEHALEM,MOVBE,SM
;# Sign and zero extension ;# Sign and zero extension
CBW void [ o16 98] 8086 CBW void [ o16 98] 8086