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travis: unbreak the ret.asm test
The ret.asm test was broken because the assembly expected -DERROR=1 whereas the run script provided -DERROR, masking all the actual errors... Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
This commit is contained in:
@@ -1 +1,6 @@
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./travis/test/ret.asm:18: error: expression syntax error
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./travis/test/ret.asm:16: error: instruction not supported in 16-bit mode
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./travis/test/ret.asm:17: error: instruction not supported in 16-bit mode
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./travis/test/ret.asm:18: error: instruction not supported in 16-bit mode
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./travis/test/ret.asm:56: error: instruction not supported in 16-bit mode
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./travis/test/ret.asm:57: error: instruction not supported in 16-bit mode
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./travis/test/ret.asm:58: error: instruction not supported in 16-bit mode
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@@ -1 +1,6 @@
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./travis/test/ret.asm:37: error: expression syntax error
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./travis/test/ret.asm:35: error: instruction not supported in 32-bit mode
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./travis/test/ret.asm:36: error: instruction not supported in 32-bit mode
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./travis/test/ret.asm:37: error: instruction not supported in 32-bit mode
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./travis/test/ret.asm:56: error: instruction not supported in 32-bit mode
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./travis/test/ret.asm:57: error: instruction not supported in 32-bit mode
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./travis/test/ret.asm:58: error: instruction not supported in 32-bit mode
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@@ -1 +1,2 @@
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./travis/test/ret.asm:53: error: expression syntax error
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./travis/test/ret.asm:51: error: instruction not supported in 64-bit mode
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./travis/test/ret.asm:52: error: instruction not supported in 64-bit mode
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@@ -1,7 +1,4 @@
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;; All the flavors of RET
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%ifndef ERROR
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%define ERROR 0
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%endif
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%ifdef TEST_BITS_16
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bits 16
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@@ -15,7 +12,7 @@
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retd
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retnd
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retfd
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%if ERROR
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%ifdef ERROR
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retq
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retnq
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retfq
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@@ -34,7 +31,7 @@
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retd
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retnd
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retfd
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%if ERROR
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%ifdef ERROR
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retq
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retnq
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retfq
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@@ -50,7 +47,7 @@
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retw
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retnw
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retfw
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%if ERROR
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%ifdef ERROR
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retd
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retnd
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%endif
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