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isnsn.dat: remove unnecessary SM from PSHUF* instructions

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The MMX and early SSE PSHUF* instructions were annotated SM0-1, which
is unnecessary (no ambiguity) but broke the tighter SM matching the
assembler now uses.

This is almost certainly underspecified now, but the MMX and early SSE
instruction patterns need to be tidied up anyway, and this is the
least impactful change that seems to fix the problem.

This unbreaks compiling ffmpeg.

Reported-by: Yongjie Sheng (Intel) <sheng.yongjie@outlook.com>
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
This commit is contained in:
H. Peter Anvin
2025-09-23 15:45:42 -07:00
parent ad6752e3e1
commit af40cc63d2
2 changed files with 14 additions and 13 deletions
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1
test/pshuf.asm Normal file
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@@ -0,0 +1 @@
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD> <EFBFBD> <EFBFBD><EFBFBD>p<EFBFBD>p<EFBFBD>ppppfp<EFBFBD>fp<EFBFBD>fpfpfpfp

12
x86/insns.dat
View File

@@ -853,7 +853,7 @@ PCMPEQW mmxreg,mmxrm [rm: np 0f 75 /r] PENT,MMX,SQ
PCMPGTB mmxreg,mmxrm [rm: np 0f 64 /r] PENT,MMX,SQ PCMPGTB mmxreg,mmxrm [rm: np 0f 64 /r] PENT,MMX,SQ
PCMPGTD mmxreg,mmxrm [rm: np 0f 66 /r] PENT,MMX,SQ PCMPGTD mmxreg,mmxrm [rm: np 0f 66 /r] PENT,MMX,SQ
PCMPGTW mmxreg,mmxrm [rm: np 0f 65 /r] PENT,MMX,SQ PCMPGTW mmxreg,mmxrm [rm: np 0f 65 /r] PENT,MMX,SQ
PDISTIB mmxreg,mem [rm: 0f 54 /r] PENT,MMX,SM,CYRIX PDISTIB mmxreg,mem [rm: 0f 54 /r] PENT,MMX,SQ,CYRIX
PF2ID mmxreg,mmxrm [rm: 0f 0f /r 1d] PENT,3DNOW,SQ PF2ID mmxreg,mmxrm [rm: 0f 0f /r 1d] PENT,3DNOW,SQ
PFACC mmxreg,mmxrm [rm: 0f 0f /r ae] PENT,3DNOW,SQ PFACC mmxreg,mmxrm [rm: 0f 0f /r ae] PENT,3DNOW,SQ
PFADD mmxreg,mmxrm [rm: 0f 0f /r 9e] PENT,3DNOW,SQ PFADD mmxreg,mmxrm [rm: 0f 0f /r 9e] PENT,3DNOW,SQ
@@ -871,7 +871,7 @@ PFRSQRT mmxreg,mmxrm [rm: 0f 0f /r 97] PENT,3DNOW,SQ
PFSUB mmxreg,mmxrm [rm: 0f 0f /r 9a] PENT,3DNOW,SQ PFSUB mmxreg,mmxrm [rm: 0f 0f /r 9a] PENT,3DNOW,SQ
PFSUBR mmxreg,mmxrm [rm: 0f 0f /r aa] PENT,3DNOW,SQ PFSUBR mmxreg,mmxrm [rm: 0f 0f /r aa] PENT,3DNOW,SQ
PI2FD mmxreg,mmxrm [rm: 0f 0f /r 0d] PENT,3DNOW,SQ PI2FD mmxreg,mmxrm [rm: 0f 0f /r 0d] PENT,3DNOW,SQ
PMACHRIW mmxreg,mem [rm: 0f 5e /r] PENT,MMX,SM,CYRIX PMACHRIW mmxreg,mem [rm: 0f 5e /r] PENT,MMX,SQ,CYRIX
PMADDWD mmxreg,mmxrm [rm: np 0f f5 /r] PENT,MMX,SQ PMADDWD mmxreg,mmxrm [rm: np 0f f5 /r] PENT,MMX,SQ
PMAGW mmxreg,mmxrm [rm: 0f 52 /r] PENT,MMX,SQ,CYRIX PMAGW mmxreg,mmxrm [rm: 0f 52 /r] PENT,MMX,SQ,CYRIX
PMULHRIW mmxreg,mmxrm [rm: 0f 5d /r] PENT,MMX,SQ,CYRIX PMULHRIW mmxreg,mmxrm [rm: 0f 5d /r] PENT,MMX,SQ,CYRIX
@@ -1139,7 +1139,7 @@ PMINUB mmxreg,mmxrm [rm: np 0f da /r] KATMAI,MMX,SQ
PMOVMSKB reg32,mmxreg [rm: np 0f d7 /r] KATMAI,MMX PMOVMSKB reg32,mmxreg [rm: np 0f d7 /r] KATMAI,MMX
PMULHUW mmxreg,mmxrm [rm: np 0f e4 /r] KATMAI,MMX,SQ PMULHUW mmxreg,mmxrm [rm: np 0f e4 /r] KATMAI,MMX,SQ
PSADBW mmxreg,mmxrm [rm: np 0f f6 /r] KATMAI,MMX,SQ PSADBW mmxreg,mmxrm [rm: np 0f f6 /r] KATMAI,MMX,SQ
PSHUFW mmxreg,mmxrm,imm [rmi: np 0f 70 /r ib] KATMAI,MMX,SM0-1,SB,AR2 PSHUFW mmxreg,mmxrm,imm [rmi: np 0f 70 /r ib] KATMAI,MMX,SB,AR2
;# AMD Enhanced 3DNow! (Athlon) instructions ;# AMD Enhanced 3DNow! (Athlon) instructions
PF2IW mmxreg,mmxrm [rm: 0f 0f /r 1c] PENT,3DNOW,SQ PF2IW mmxreg,mmxrm [rm: 0f 0f /r 1c] PENT,3DNOW,SQ
@@ -1217,11 +1217,11 @@ PMULUDQ xmmreg,xmmrm [rm: 66 0f f4 /r] WILLAMETTE,SSE2,SO
POR xmmreg,xmmrm [rm: 66 0f eb /r] WILLAMETTE,SSE2,SO POR xmmreg,xmmrm [rm: 66 0f eb /r] WILLAMETTE,SSE2,SO
PSADBW xmmreg,xmmrm [rm: 66 0f f6 /r] WILLAMETTE,SSE2,SO PSADBW xmmreg,xmmrm [rm: 66 0f f6 /r] WILLAMETTE,SSE2,SO
PSHUFD xmmreg,xmmreg,imm [rmi: 66 0f 70 /r ib] WILLAMETTE,SSE2,SB,AR2 PSHUFD xmmreg,xmmreg,imm [rmi: 66 0f 70 /r ib] WILLAMETTE,SSE2,SB,AR2
PSHUFD xmmreg,mem,imm [rmi: 66 0f 70 /r ib] WILLAMETTE,SSE2,SM0-1,SB,AR2 PSHUFD xmmreg,mem,imm [rmi: 66 0f 70 /r ib] WILLAMETTE,SSE2,SB,AR2
PSHUFHW xmmreg,xmmreg,imm [rmi: f3 0f 70 /r ib] WILLAMETTE,SSE2,SB,AR2 PSHUFHW xmmreg,xmmreg,imm [rmi: f3 0f 70 /r ib] WILLAMETTE,SSE2,SB,AR2
PSHUFHW xmmreg,mem,imm [rmi: f3 0f 70 /r ib] WILLAMETTE,SSE2,SM0-1,SB,AR2 PSHUFHW xmmreg,mem,imm [rmi: f3 0f 70 /r ib] WILLAMETTE,SSE2,SB,AR2
PSHUFLW xmmreg,xmmreg,imm [rmi: f2 0f 70 /r ib] WILLAMETTE,SSE2,SB,AR2 PSHUFLW xmmreg,xmmreg,imm [rmi: f2 0f 70 /r ib] WILLAMETTE,SSE2,SB,AR2
PSHUFLW xmmreg,mem,imm [rmi: f2 0f 70 /r ib] WILLAMETTE,SSE2,SM0-1,SB,AR2 PSHUFLW xmmreg,mem,imm [rmi: f2 0f 70 /r ib] WILLAMETTE,SSE2,SB,AR2
PSLLDQ xmmreg,imm [mi: 66 0f 73 /7 ib,u] WILLAMETTE,SSE2,SB,AR1 PSLLDQ xmmreg,imm [mi: 66 0f 73 /7 ib,u] WILLAMETTE,SSE2,SB,AR1
PSLLW xmmreg,xmmrm [rm: 66 0f f1 /r] WILLAMETTE,SSE2,SO PSLLW xmmreg,xmmrm [rm: 66 0f f1 /r] WILLAMETTE,SSE2,SO
PSLLW xmmreg,imm [mi: 66 0f 71 /6 ib,u] WILLAMETTE,SSE2,SB,AR1 PSLLW xmmreg,imm [mi: 66 0f 71 /6 ib,u] WILLAMETTE,SSE2,SB,AR1