test: nasm-t -- Add pinsr test

Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>

travis/test/pinsr.json

@@ -0,0 +1,29 @@
+[
+	{
+		"description": "Test pinsr instruction in 16 bit mode",
+		"format": "bin",
+		"source": "pinsr16.asm",
+		"option": "-O0",
+		"target": [
+			{ "output": "pinsr16.bin" }
+		]
+	},
+	{
+		"description": "Test pinsr instruction in 32 bit mode",
+		"format": "bin",
+		"source": "pinsr32.asm",
+		"option": "-O0",
+		"target": [
+			{ "output": "pinsr32.bin" }
+		]
+	},
+	{
+		"description": "Test pinsr instruction in 64 bit mode",
+		"format": "bin",
+		"source": "pinsr64.asm",
+		"option": "-O0",
+		"target": [
+			{ "output": "pinsr64.bin" }
+		]
+	}
+]

travis/test/pinsr16.asm

@@ -0,0 +1,52 @@
+	bits 16
+
+	pinsrw mm0,eax,0
+	pinsrw mm1,si,0
+	pinsrw mm2,[bx],0
+	pinsrw mm3,word [bx],0
+
+	pinsrb xmm0,eax,0
+	pinsrb xmm1,sil,0
+;	pinsrb xmm1,bh,0
+	pinsrb xmm2,[bx],0
+	pinsrb xmm3,byte [bx],0
+
+	pinsrw xmm0,eax,0
+	pinsrw xmm1,si,0
+	pinsrw xmm2,[bx],0
+	pinsrw xmm3,word [bx],0
+
+	pinsrd xmm0,eax,0
+	pinsrd xmm1,esi,0
+	pinsrd xmm2,[bx],0
+	pinsrd xmm3,dword [bx],0
+
+	vpinsrb xmm0,eax,0
+	vpinsrb xmm1,bl,0
+	vpinsrb xmm2,[bx],0
+	vpinsrb xmm3,byte [bx],0
+
+	vpinsrw xmm0,eax,0
+	vpinsrw xmm1,si,0
+	vpinsrw xmm2,[bx],0
+	vpinsrw xmm3,word [bx],0
+
+	vpinsrd xmm0,eax,0
+	vpinsrd xmm1,esi,0
+	vpinsrd xmm2,[bx],0
+	vpinsrd xmm3,dword [bx],0
+
+	vpinsrb xmm4,xmm0,eax,0
+	vpinsrb xmm5,xmm1,bl,0
+	vpinsrb xmm6,xmm2,[bx],0
+	vpinsrb xmm7,xmm3,byte [bx],0
+
+	vpinsrw xmm4,xmm0,eax,0
+	vpinsrw xmm5,xmm1,si,0
+	vpinsrw xmm6,xmm2,[bx],0
+	vpinsrw xmm7,xmm3,word [bx],0
+
+	vpinsrd xmm4,xmm0,eax,0
+	vpinsrd xmm5,xmm1,esi,0
+	vpinsrd xmm6,xmm2,[bx],0
+	vpinsrd xmm7,xmm3,dword [bx],0

travis/test/pinsr32.asm

@@ -0,0 +1,52 @@
+	bits 32
+
+	pinsrw mm0,eax,0
+	pinsrw mm1,si,0
+	pinsrw mm2,[ecx],0
+	pinsrw mm3,word [ecx],0
+
+	pinsrb xmm0,eax,0
+	pinsrb xmm1,sil,0
+;	pinsrb xmm1,bh,0
+	pinsrb xmm2,[ecx],0
+	pinsrb xmm3,byte [ecx],0
+
+	pinsrw xmm0,eax,0
+	pinsrw xmm1,si,0
+	pinsrw xmm2,[ecx],0
+	pinsrw xmm3,word [ecx],0
+
+	pinsrd xmm0,eax,0
+	pinsrd xmm1,esi,0
+	pinsrd xmm2,[ecx],0
+	pinsrd xmm3,dword [ecx],0
+
+	vpinsrb xmm0,eax,0
+	vpinsrb xmm1,bl,0
+	vpinsrb xmm2,[ecx],0
+	vpinsrb xmm3,byte [ecx],0
+
+	vpinsrw xmm0,eax,0
+	vpinsrw xmm1,si,0
+	vpinsrw xmm2,[ecx],0
+	vpinsrw xmm3,word [ecx],0
+
+	vpinsrd xmm0,eax,0
+	vpinsrd xmm1,esi,0
+	vpinsrd xmm2,[ecx],0
+	vpinsrd xmm3,dword [ecx],0
+
+	vpinsrb xmm4,xmm0,eax,0
+	vpinsrb xmm5,xmm1,bl,0
+	vpinsrb xmm6,xmm2,[ecx],0
+	vpinsrb xmm7,xmm3,byte [ecx],0
+
+	vpinsrw xmm4,xmm0,eax,0
+	vpinsrw xmm5,xmm1,si,0
+	vpinsrw xmm6,xmm2,[ecx],0
+	vpinsrw xmm7,xmm3,word [ecx],0
+
+	vpinsrd xmm4,xmm0,eax,0
+	vpinsrd xmm5,xmm1,esi,0
+	vpinsrd xmm6,xmm2,[ecx],0
+	vpinsrd xmm7,xmm3,dword [ecx],0

travis/test/pinsr64.asm

@@ -0,0 +1,67 @@
+	bits 64
+
+	pinsrw mm0,eax,0
+	pinsrw mm1,si,0
+	pinsrw mm2,[rcx],0
+	pinsrw mm3,word [rcx],0
+
+	pinsrb xmm0,eax,0
+	pinsrb xmm1,sil,0
+;	pinsrb xmm1,bh,0
+	pinsrb xmm2,[rcx],0
+	pinsrb xmm3,byte [rcx],0
+
+	pinsrw xmm0,eax,0
+	pinsrw xmm1,si,0
+	pinsrw xmm2,[rcx],0
+	pinsrw xmm3,word [rcx],0
+
+	pinsrd xmm0,eax,0
+	pinsrd xmm1,esi,0
+	pinsrd xmm2,[rcx],0
+	pinsrd xmm3,dword [rcx],0
+
+	pinsrq xmm0,rax,0
+	pinsrq xmm1,rsi,0
+	pinsrq xmm2,[rcx],0
+	pinsrq xmm3,qword [rcx],0
+
+	vpinsrb xmm0,eax,0
+	vpinsrb xmm1,sil,0
+	vpinsrb xmm2,[rcx],0
+	vpinsrb xmm3,byte [rcx],0
+
+	vpinsrw xmm0,eax,0
+	vpinsrw xmm1,si,0
+	vpinsrw xmm2,[rcx],0
+	vpinsrw xmm3,word [rcx],0
+
+	vpinsrd xmm0,eax,0
+	vpinsrd xmm1,esi,0
+	vpinsrd xmm2,[rcx],0
+	vpinsrd xmm3,dword [rcx],0
+
+	vpinsrq xmm0,rax,0
+	vpinsrq xmm1,rsi,0
+	vpinsrq xmm2,[rcx],0
+	vpinsrq xmm3,qword [rcx],0
+
+	vpinsrb xmm4,xmm0,eax,0
+	vpinsrb xmm5,xmm1,sil,0
+	vpinsrb xmm6,xmm2,[rcx],0
+	vpinsrb xmm7,xmm3,byte [rcx],0
+
+	vpinsrw xmm4,xmm0,eax,0
+	vpinsrw xmm5,xmm1,si,0
+	vpinsrw xmm6,xmm2,[rcx],0
+	vpinsrw xmm7,xmm3,word [rcx],0
+
+	vpinsrd xmm4,xmm0,eax,0
+	vpinsrd xmm5,xmm1,esi,0
+	vpinsrd xmm6,xmm2,[rcx],0
+	vpinsrd xmm7,xmm3,dword [rcx],0
+
+	vpinsrq xmm4,xmm0,rax,0
+	vpinsrq xmm5,xmm1,rsi,0
+	vpinsrq xmm6,xmm2,[rcx],0
+	vpinsrq xmm7,xmm3,qword [rdx],0