From 7ad24f65818545b6541ad48e33dee40c4be01182 Mon Sep 17 00:00:00 2001 From: Debbie Wiles Date: Fri, 17 May 2002 00:14:58 +0000 Subject: [PATCH] Corrected uD# documentation --- doc/nasmdoc.src | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/doc/nasmdoc.src b/doc/nasmdoc.src index daa2ee52..d4e20c6a 100644 --- a/doc/nasmdoc.src +++ b/doc/nasmdoc.src @@ -12541,14 +12541,14 @@ purposes. \c{UD0} is specifically documented by AMD as being reserved for this purpose. -\c{UD1} is specifically documented by Intel as being reserved for this -purpose. +\c{UD1} is documented by Intel as being available for this purpose. -\c{UD2} is mentioned by Intel as being available, but is not mentioned -as reserved. +\c{UD2} is specifically documented by Intel as being reserved for this +purpose. Intel document this as the preferred method of generating an +invalid opcode exception. All these opcodes can be used to generate invalid opcode exceptions on -all processors that are available at the current time. +all currently available processors. \S{insUMOV} \i\c{UMOV}: User Move Data