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insns.pl: sanity-check that instruction encodings match operands
Error out if an encoding position is invalid, like an "r" operand matches an "xmmrm" operand. Document the instruction encoding symbols; there are too many of them by now. Add symbols 'n' and 'w' meaning immediates that are supposed to be encoded as if they were 'm' memory addresses and 'v' register numbers, respectively; this is necessary to indicate a validation exception. Remove broken ARPL "memory-like" encoding. It probably never worked anyway. This verification caught two bugs already: - VPMASKMOV[DQ] cannot omit the second operand. - Incorrect operand encoding order for VREDUCESH. Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
This commit is contained in:
H. Peter Anvin
@@ -7,8 +7,22 @@ and consumed by asm/assemble.c and disasm/disasm.c.
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Values prefixed with \ are in octal, values prefixed with \x are in
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hexadecimal.
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The mnemonics are the ones used in x86/insns.txt, where applicable.
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The mnemonics are the ones used in x86/insns.dat, where applicable.
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In x86/insns.dat, the encoding slot of each operand is encoded as:
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- implicit operand (no encoding)
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x+y multiple encoding slots for one operand
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r "r" position in modr/m, or base register with "+r"
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m "m" position in modr/m
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n immediate encoded in the "m" position in modr/m
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b register encoded in the "m" position in modr/m
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x register encoded in the "x" position in modr/m + sib (MIB)
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v "v" register position in vex/evex
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s "s" registe rposition in /is4
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w immediate encoded in the "v" position in vex/evex
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i first immediate or mem_offs
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j second immediate or mem_offs
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Codes Mnemonic Explanation
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@@ -96,7 +96,7 @@ $bwdq MOVRS reg#,mem# [rm: evex.nf0.nd0.l0.m4.o# 8a# /r] FUTURE,SM
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;# Load effective address
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$wdq LEA reg#,mem [rm: o# 8d /r] 8086
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$wdq LEA reg#,imm# [rm: o# 8d /r] 8086,ND
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$wdq LEA reg#,imm# [rn: o# 8d /r] 8086,ND
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;# The basic 8 arithmetic operations
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$arith nf=nf ADD OR nf=,ADC nf=,SBB AND SUB XOR nf=,!evex,CMP
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@@ -448,7 +448,7 @@ WBNOINVD void [ f3 0f 09] WBNOINVD,PRIV
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INVPCID reg32,mem128 [rm: 66 0f38 82 /r] INVPCID,PRIV,NOLONG
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INVPCID reg64,mem128 [rm: 66 0f38 82 /r] INVPCID,PRIV,LONG
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INVPCID reg64,mem128 [rm: evex.nf0.nd0.l0.f3.m4.w1 f2 /r] APX,INVPCID,PRIV,LONG
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INVPCID reg64,mem128 [rm: evex.nf0.nd0.l0.f3.m4.w1 f2 /r] APX,INVPCID,PRIV,LONG
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INVLPG mem [m: 0f 01 /7] 486,PRIV
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$wdq INVLPGA ax#,reg_ecx [--: a# 0f 01 df] X86_64,AMD
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INVLPGA void [ adf 0f 01 df] X86_64,AMD,ND
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@@ -578,7 +578,7 @@ $dq RDGSBASE reg# [m: w# f3 0f ae /1] LONG
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$dq WRFSBASE reg# [m: w# f3 0f ae /2] LONG
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$dq WRGSBASE reg# [m: w# f3 0f ae /3] LONG
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$zwd ARPL rm16,sel# [mr: optw# 63 /r] 286,PROT,SM,NOLONG
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$wd ARPL rm16,reg# [mr: optw# 63 /r] 286,PROT,SM,NOLONG
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$wdq LAR reg#,rm_sel [rm: optd# 0f 02 /r] 286,PROT
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$wdq LSL reg#,rm_sel [rm: optd# 0f 03 /r] 286,PROT
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@@ -984,14 +984,14 @@ FWAIT void [ wait] 8086
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XLATB void [ d7] 8086
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XLAT void [ d7] 8086,ND
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$bwdq CCMPscc spec4,rm#,reg# [vmr: evex.scc.dfv.l0.m4.o# 38# /r ] APX,SM1-2
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$bwdq CCMPscc spec4,reg#,rm# [vrm: evex.scc.dfv.l0.m4.o# 3a# /r ] APX,SM1-2
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$wdq CCMPscc spec4,rm#,sbyte# [vmi: evex.scc.dfv.l0.m4.o# 83 /7 ib,s ] APX,SM1-2
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$bwdq CCMPscc spec4,rm#,imm# [vmi: evex.scc.dfv.l0.m4.o# 80# /7 i# ] APX,SM1-2
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$bwdq CCMPscc spec4,rm#,reg# [wmr: evex.scc.dfv.l0.m4.o# 38# /r ] APX,SM1-2
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$bwdq CCMPscc spec4,reg#,rm# [wrm: evex.scc.dfv.l0.m4.o# 3a# /r ] APX,SM1-2
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$wdq CCMPscc spec4,rm#,sbyte# [wmi: evex.scc.dfv.l0.m4.o# 83 /7 ib,s ] APX,SM1-2
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$bwdq CCMPscc spec4,rm#,imm# [wmi: evex.scc.dfv.l0.m4.o# 80# /7 i# ] APX,SM1-2
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$bwdq CTESTscc spec4,rm#,reg# [vmr: evex.scc.dfv.l0.m4.o# 84# /r ] APX,SM1-2
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$bwdq CTESTscc spec4,rm#,imm# [vmi: evex.scc.dfv.l0.m4.o# f6# /0 i# ] APX,SM1-2
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$bwdq CTESTscc spec4,rm#,imm# [vmi: evex.scc.dfv.l0.m4.o# f6# /1 i# ] APX,SM1-2
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$bwdq CTESTscc spec4,rm#,reg# [wmr: evex.scc.dfv.l0.m4.o# 84# /r ] APX,SM1-2
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$bwdq CTESTscc spec4,rm#,imm# [wmi: evex.scc.dfv.l0.m4.o# f6# /0 i# ] APX,SM1-2
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$bwdq CTESTscc spec4,rm#,imm# [wmi: evex.scc.dfv.l0.m4.o# f6# /1 i# ] APX,SM1-2
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;# Conditional instructions
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$wdq CMOVcc reg#,rm# [rm: o# 0f 40+c /r] P6,SM
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@@ -2957,10 +2957,10 @@ VPMASKMOVD ymmreg,ymmreg*,mem256 [rvm: vex.nds.256.66.0f38.w0 8c /r] AVX2
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VPMASKMOVQ xmmreg,xmmreg*,mem128 [rvm: vex.nds.128.66.0f38.w1 8c /r] AVX2
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VPMASKMOVQ ymmreg,ymmreg*,mem256 [rvm: vex.nds.256.66.0f38.w1 8c /r] AVX2
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VPMASKMOVD mem128,xmmreg*,xmmreg [mvr: vex.nds.128.66.0f38.w0 8e /r] AVX2
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VPMASKMOVD mem256,ymmreg*,ymmreg [mvr: vex.nds.256.66.0f38.w0 8e /r] AVX2
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VPMASKMOVQ mem128,xmmreg*,xmmreg [mvr: vex.nds.128.66.0f38.w1 8e /r] AVX2
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VPMASKMOVQ mem256,ymmreg*,ymmreg [mvr: vex.nds.256.66.0f38.w1 8e /r] AVX2
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VPMASKMOVD mem128,xmmreg,xmmreg [mvr: vex.nds.128.66.0f38.w0 8e /r] AVX2
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VPMASKMOVD mem256,ymmreg,ymmreg [mvr: vex.nds.256.66.0f38.w0 8e /r] AVX2
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VPMASKMOVQ mem128,xmmreg,xmmreg [mvr: vex.nds.128.66.0f38.w1 8e /r] AVX2
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VPMASKMOVQ mem256,ymmreg,ymmreg [mvr: vex.nds.256.66.0f38.w1 8e /r] AVX2
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VPSLLVD xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f38.w0 47 /r] AVX2
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VPSLLVQ xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f38.w1 47 /r] AVX2
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@@ -5749,7 +5749,7 @@ VRCPSH xmmreg|mask|z,xmmreg*,xmmrm16|sae [rvm:t1s: evex.nds.lig.66.map6.w0 4d /
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VREDUCEPH xmmreg|mask|z,xmmrm128|b16,imm8 [rmi:fv: evex.128.np.0f3a.w0 56 /r ib] AVX512FP16,AVX512VL
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VREDUCEPH ymmreg|mask|z,ymmrm256|b16,imm8 [rmi:fv: evex.256.np.0f3a.w0 56 /r ib] AVX512FP16,AVX512VL
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VREDUCEPH zmmreg|mask|z,zmmrm512|b16|sae,imm8 [rmi:fv: evex.512.np.0f3a.w0 56 /r ib] AVX512FP16
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VREDUCESH xmmreg|mask|z,xmmreg*,xmmrm16|sae,imm8 [rmvi:t1s: evex.nds.lig.np.0f3a.w0 57 /r ib] AVX512FP16
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VREDUCESH xmmreg|mask|z,xmmreg*,xmmrm16|sae,imm8 [rvmi:t1s: evex.nds.lig.np.0f3a.w0 57 /r ib] AVX512FP16
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VENDSCALEPH xmmreg|mask|z,xmmrm128|b16,imm8 [rmi:fv: evex.128.np.0f3a.w0 08 /r ib] AVX512FP16,AVX512VL
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VENDSCALEPH ymmreg|mask|z,ymmrm256|b16,imm8 [rmi:fv: evex.256.np.0f3a.w0 08 /r ib] AVX512FP16,AVX512VL
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VENDSCALEPH zmmreg|mask|z,zmmrm512|b16|sae,imm8 [rmi:fv: evex.512.np.0f3a.w0 08 /r ib] AVX512FP16
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130
x86/insns.pl
130
x86/insns.pl
@@ -118,7 +118,7 @@ sub startseq($$) {
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my $enc = 0; # Legacy
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my $map = 0; # Map 0
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@codes = decodify(undef, $codestr, {});
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@codes = decodify(undef, $codestr, {}, undef);
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while (defined($c0 = shift(@codes))) {
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$c1 = $codes[0]; # The immediate following code
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@@ -740,7 +740,7 @@ sub format_insn($$$$) {
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my ($num, $flagsindex);
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my @bytecode;
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my ($op, @ops, @opsize, $opp, @opx, @oppx, @decos, @opevex);
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my %oppos;
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my $opinfo;
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return (undef, undef) if $operands eq 'ignore';
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@@ -751,7 +751,8 @@ sub format_insn($$$$) {
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set_implied_flags(\%flags);
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# Generate byte code. This may modify the flags.
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@bytecode = (decodify($opcode, $codes, \%flags, \%oppos), 0);
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@bytecode = (decodify($opcode, $codes, \%flags, \$opinfo), 0);
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my($oppos, $openc) = @$opinfo;
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push(@bytecode_list, [@bytecode]);
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$codes = hexstr(@bytecode);
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count_bytecodes(@bytecode);
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@@ -766,8 +767,13 @@ sub format_insn($$$$) {
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@opsize = ();
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@decos = ();
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if ($operands ne 'void') {
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my $opnum = scalar(@ops);
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foreach $op (split(/,/, $operands)) {
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my $opnum = scalar(@ops);
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my $isreg = 0;
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my $ismem = 0;
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my $ismoffs = 0;
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my $isimm = 0;
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my $isrm = 0;
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my $iszero = 0;
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my $opsz = 0;
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@opx = ();
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@@ -778,6 +784,8 @@ sub format_insn($$$$) {
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push(@opevex, $1);
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}
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$opp =~ s/^reg([0-9]*)na$/reg_na$1/;
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if ($opp =~ s/([^0-9]0?)(8|16|32|64|80|128|256|512|1024|1k)$/$1/) {
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push(@oppx, "bits$2");
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$opsz = $1 + 0;
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@@ -789,35 +797,68 @@ sub format_insn($$$$) {
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$opp .= 'reg';
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}
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}
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$opp =~ s/^mem$/memory/;
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$opp =~ s/^memory_offs$/mem_offs/;
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$opp =~ s/^mem$/memory/;
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if ($opp =~ s/^(spec|imm)4$/$1/) {
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push(@oppx, 'fourbits');
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$isimm = 1;
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}
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$opp =~ s/^spec$/immediate/; # Immediate or special immediate
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$opp =~ s/^imm$/imm_normal/; # Normal immediates only
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$opp =~ s/^spec$/immediate/; # Special or normal immediate
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$opp =~ s/^imm$/imm_normal/; # Normal immediate only
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if ($opp =~ /^(unity|sbyted?word|[su]dword)$/) {
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push(@oppx, 'imm_normal');
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$isimm = 1;
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}
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if ($opp =~ /^imm/) {
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$isimm = 1;
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}
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$opp =~ s/^([a-z]+)rm$/rm_$1/;
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$opp =~ s/^(rm|reg)$/$1_gpr/;
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$opp =~ s/^rm_k$/rm_opmask/;
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$opp =~ s/^kreg$/opmaskreg/;
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my $isreg = ($opp =~ /(\brm_|\breg_|reg\b)/);
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my $isrm = $isreg || ($opp =~ /\bmem/);
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my $isvec = ($opp =~ /\b[xyzt]mm/);
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if ($isrm &&
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if ($opp =~ /\brm_/) {
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$isrm = 1;
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} elsif ($opp =~ /(\breg_|reg\b)/) {
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$isreg = 1;
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} elsif ($opp =~ /\b[xyzt]?mem/) {
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$ismem = 1;
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}
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if ($opp =~ /\bmem_offs/) {
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$ismoffs = 1;
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}
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if ($opp =~ /\b[xyzt]mm/) {
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$isvec = 1;
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}
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if (($isrm || ($ismem && !$ismoffs) || $isreg) &&
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!(($flags{'EVEX'} && $isvec) || !$flags{'NOAPX'})) {
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# Register numbers >= 16 disallowed
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push(@oppx, 'rn_l16');
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}
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if ($isreg && $isvec &&
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defined($oppos->{'b'}) && $opnum == $oppos->{'b'}) {
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if ($isreg && $isvec && $openc->[$opnum] =~ /b/) {
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$flags{'MOPVEC'}++;
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}
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push(@opx, $opp, @oppx) if $opp;
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}
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$op = join('|', @opx);
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# Sanity-check the encoding of this operand
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my $opvalid = '-';
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if ($isreg) {
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$opvalid .= 'rvmsbx';
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} elsif ($isimm || $ismoffs) {
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$opvalid .= 'ijnw';
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} elsif ($ismem || $isrm) {
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$opvalid .= 'm';
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}
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foreach my $c (split(//, $openc->[$opnum])) {
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if (index($opvalid, $c) < 0) {
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die "$fname:$line: $opcode: operand $opnum \"$op\": '$c' must be one of '$opvalid'\n";
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}
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}
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$op = join('|',@opx);
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push(@ops, $op);
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push(@opsize, $opsz);
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push(@decos, (@opevex ? join('|', @opevex) : '0'));
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@@ -954,17 +995,17 @@ sub show_iflags($) {
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#
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# Turn a code string into a sequence of bytes
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#
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sub decodify($$$) {
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sub decodify($$$$) {
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# Although these are C-syntax strings, by convention they should have
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# only octal escapes (for directives) and hexadecimal escapes
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# (for verbatim bytes)
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my($opcode, $codestr, $flags) = @_;
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my($opcode, $codestr, $flags, $opinfo) = @_;
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my @codes;
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if ($codestr eq 'ignore') {
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@codes = ();
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} elsif ($codestr =~ /^\s*\[([^\]]*)\]\s*$/) {
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@codes = byte_code_compile($opcode, $1, $flags);
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@codes = byte_code_compile($opcode, $1, $flags, $opinfo);
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} else {
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# This really shouldn't happen anymore...
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warn "$fname:$line: raw bytecodes?!\n";
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@@ -1056,7 +1097,7 @@ sub tupletype($) {
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# enter it as e.g. "r+v".
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#
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sub byte_code_compile($$$$) {
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my($opcode, $str, $flags, $oppos) = @_;
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my($opcode, $str, $flags, $opinfo) = @_;
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my $opr;
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my $opc;
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my @codes = ();
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@@ -1158,14 +1199,49 @@ sub byte_code_compile($$$$) {
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$opc = lc($4);
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$op = 0;
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$oppos = {};
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my $oppos = {};
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my $openc = [];
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if (defined($opinfo)) {
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$$opinfo = [$oppos, $openc];
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}
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for ($i = 0; $i < length($opr); $i++) {
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my $c = substr($opr,$i,1);
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if ($c eq '+') {
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die "$fname:$line: $opcode: invalid use of '+' in '$opr'\n"
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if ($op < 1);
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$op--;
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} elsif ($c =~ /^[rmnvwsijbx-]$/) {
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# n means an immediate which is encoded as a memory address,
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# but unlike a mem_offs it supports rel encoding on 64 bits.
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# w means an immediate to be encoded into the v register
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# position.
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(my $realc = $c) =~ tr/nw/mv/;
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$openc->[$op] = '' unless (defined($openc->[$op]));
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$openc->[$op] .= $c;
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if (defined($oppos->{$realc})) {
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my $what = ($c eq $realc) ? "'$c'" : "[${realc}${c}]";
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die "$fname:$line: $opcode: More than one $what operand in '$opr'\n";
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}
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$oppos->{$realc} = $op unless ($realc eq '-');
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$op++;
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} else {
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$oppos->{$c} = $op++;
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}
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die "$fname:$line: $opcode: Unknown operand encoding '$c'\n";
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}
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}
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if (defined($oppos->{'m'})) {
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if (defined($oppos->{'b'})) {
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die "$fname:$line: $opcode: [mn] operand mutually exclusive with 'b'\n";
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} elsif (defined($oppos->{'x'})) {
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# memory operand + x register operand requires MIB
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$flags->{'MIB'}++;
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}
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}
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if (defined($oppos->{'s'}) && defined($oppos->{'i'})) {
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die "$fname:$line: $opcode: 's' operand mutually exclusive with 'i'\n";
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}
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if (defined($oppos->{'j'}) && !defined($oppos->{'i'})) {
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die "$fname:$line: $opcode 'j' without 'i' operand\n";
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}
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$tup = tupletype($tuple);
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@@ -1223,7 +1299,7 @@ sub byte_code_compile($$$$) {
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$prefix_ok = 0;
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} elsif ($op eq '/r') {
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if (!defined($oppos->{'r'}) || !defined($oppos->{'m'})) {
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die "$fname:$line: $opcode: $op requires r and m operands\n";
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die "$fname:$line: $opcode: $op requires 'r' and [mn] operands\n";
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}
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$opex = (($oppos->{'m'} & 4) ? 06 : 0) |
|
||||
(($oppos->{'r'} & 4) ? 05 : 0);
|
||||
@@ -1234,14 +1310,14 @@ sub byte_code_compile($$$$) {
|
||||
$prefix_ok = 0;
|
||||
} elsif ($op =~ m:^/([0-7])$:) {
|
||||
if (!defined($oppos->{'m'})) {
|
||||
die "$fname:$line: $opcode: $op requires an m operand\n";
|
||||
die "$fname:$line: $opcode: $op requires an [mn] operand\n";
|
||||
}
|
||||
push(@codes, 06) if ($oppos->{'m'} & 4);
|
||||
push(@codes, 0200 + (($oppos->{'m'} & 3) << 3) + $1);
|
||||
$prefix_ok = 0;
|
||||
} elsif ($op =~ m:^/([0-3]?)r([0-7])$:) {
|
||||
if (!defined($oppos->{'r'})) {
|
||||
die "$fname:$line: $opcode: $op requires an r operand\n";
|
||||
die "$fname:$line: $opcode: $op requires an 'r' operand\n";
|
||||
}
|
||||
push(@codes, 05) if ($oppos->{'r'} & 4);
|
||||
push(@codes, 0171);
|
||||
@@ -1332,7 +1408,7 @@ sub byte_code_compile($$$$) {
|
||||
$m = $2+0;
|
||||
} elsif ($oq eq 'nds' || $oq eq 'ndd' || $oq eq 'dds') {
|
||||
if (!defined($oppos->{'v'})) {
|
||||
die "$fname:$line: $opcode: $vexname.$oq without 'v' operand\n";
|
||||
die "$fname:$line: $opcode: $vexname.$oq without [vw] operand\n";
|
||||
}
|
||||
$has_nds = 1;
|
||||
} else {
|
||||
@@ -1476,7 +1552,7 @@ sub byte_code_compile($$$$) {
|
||||
$flags->{'ZU_E'}++;
|
||||
} elsif ($oq =~ /^(nds|ndd|nd|dds)$/) {
|
||||
if (!defined($oppos->{'v'})) {
|
||||
die "$fname:$line: $opcode: evex.$oq without 'v' operand\n";
|
||||
die "$fname:$line: $opcode: evex.$oq without [vw] operand\n";
|
||||
}
|
||||
$nds = 1;
|
||||
$nd = $oq eq 'nd';
|
||||
@@ -1544,7 +1620,7 @@ sub byte_code_compile($$$$) {
|
||||
} elsif (defined $imm_codes{$op}) {
|
||||
if ($op eq 'seg') {
|
||||
if ($last_imm lt 'i') {
|
||||
die "$fname:$line: $opcode: seg without an immediate operand\n";
|
||||
die "$fname:$line: $opcode: seg without an [ij] operand\n";
|
||||
}
|
||||
} else {
|
||||
$last_imm++;
|
||||
|
||||
Reference in New Issue
Block a user