From 2b4bc67d78dfad7997e9e15d35f8d2b17117c2e5 Mon Sep 17 00:00:00 2001
From: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
Date: Tue, 16 Sep 2025 11:21:52 +0200
Subject: [PATCH] travis: apx: Separate file for legacy conditional
 instructions

Split off cmovcc and cmpcc to a separate file.

Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
---
 travis/test/apx-cond.asm   | 459 +++++++++++++++++++++++++++++++++++++
 travis/test/apx-cond.bin.t | 316 +++++++++++++++++++++++++
 travis/test/apx-cond.json  |  18 ++
 travis/test/apx.asm        | 446 -----------------------------------
 travis/test/apx.bin.t      | Bin 3487 -> 1959 bytes
 5 files changed, 793 insertions(+), 446 deletions(-)
 create mode 100644 travis/test/apx-cond.asm
 create mode 100644 travis/test/apx-cond.bin.t
 create mode 100644 travis/test/apx-cond.json

diff --git a/travis/test/apx-cond.asm b/travis/test/apx-cond.asm
new file mode 100644
index 00000000..ae0d719f
--- /dev/null
+++ b/travis/test/apx-cond.asm
@@ -0,0 +1,459 @@
+; APX legacy conditional testcases
+
+%macro testcase 2
+ %ifdef BIN
+  db %1
+ %endif
+ %ifdef SRC
+  %2
+ %endif
+%endmacro
+
+bits 64
+
+; --- cmovcc - conditional move instruction ---
+; - cmovb/cmovnae/cmovc - cmov if below -
+testcase	{0x66, 0x0F, 0x42, 0x0A},		{cmovb cx, [rdx]}	; r/m16 -> reg16
+testcase	{0x0F, 0x42, 0x0A},			{cmovb ecx, [rdx]}	; r/m32 -> reg32
+testcase	{0x4C, 0x0F, 0x42, 0x0A},		{cmovb r9, [rdx]}	; r/m64 -> reg64
+testcase	{0x66, 0x0F, 0x42, 0x0A},		{cmovnae cx, [rdx]}	; r/m16 -> reg16
+testcase	{0x0F, 0x42, 0x0A},			{cmovnae ecx, [rdx]}	; r/m32 -> reg32
+testcase	{0x4C, 0x0F, 0x42, 0x0A},		{cmovnae r9, [rdx]}	; r/m64 -> reg64
+
+; implicit evex through ND
+testcase	{0x62, 0xF4, 0x35, 0x10, 0x42, 0x0A},	{cmovb r25w, cx, [rdx]}		; ndd16 = cond ? r/m16 : reg16
+testcase	{0x62, 0xF4, 0x34, 0x10, 0x42, 0x0A},	{cmovb r25d, ecx, [rdx]}	; ndd32 = cond ? r/m32 : reg32
+testcase	{0x62, 0xF4, 0xB4, 0x10, 0x42, 0x0A},	{cmovb r25, rcx, [rdx]}		; ndd64 = cond ? r/m64 : reg64
+testcase	{0x62, 0xF4, 0x35, 0x10, 0x42, 0x0A},	{cmovnae r25w, cx, [rdx]}	; ndd16 = cond ? r/m16 : reg16
+testcase	{0x62, 0xF4, 0x34, 0x10, 0x42, 0x0A},	{cmovnae r25d, ecx, [rdx]}	; ndd32 = cond ? r/m32 : reg32
+testcase	{0x62, 0xF4, 0xB4, 0x10, 0x42, 0x0A},	{cmovnae r25, rcx, [rdx]}	; ndd64 = cond ? r/m64 : reg64
+
+; rex2 variant
+testcase	{0x66, 0xD5, 0xC4, 0x42, 0x0A},		{cmovb r25w, [rdx]}	; r/m16 -> ereg16
+testcase	{0xD5, 0xC4, 0x42, 0x0A},		{cmovb r25d, [rdx]}	; r/m32 -> ereg32
+testcase	{0xD5, 0xCC, 0x42, 0x0A},		{cmovb r25, [rdx]}	; r/m64 -> ereg64
+testcase	{0x66, 0xD5, 0xC4, 0x42, 0x0A},		{cmovnae r25w, [rdx]}	; r/m16 -> ereg16
+testcase	{0xD5, 0xC4, 0x42, 0x0A},		{cmovnae r25d, [rdx]}	; r/m32 -> ereg32
+testcase	{0xD5, 0xCC, 0x42, 0x0A},		{cmovnae r25, [rdx]}	; r/m64 -> ereg64
+
+; - cmovbe/cmovna - cmov if below or equal -
+testcase	{0x66, 0x0F, 0x46, 0x0A},		{cmovbe cx, [rdx]}	; r/m16 -> reg16
+testcase	{0x0F, 0x46, 0x0A},			{cmovbe ecx, [rdx]}	; r/m32 -> reg32
+testcase	{0x4C, 0x0F, 0x46, 0x0A},		{cmovbe r9, [rdx]}	; r/m64 -> reg64
+testcase	{0x66, 0x0F, 0x46, 0x0A},		{cmovna cx, [rdx]}	; r/m16 -> reg16
+testcase	{0x0F, 0x46, 0x0A},			{cmovna ecx, [rdx]}	; r/m32 -> reg32
+testcase	{0x4C, 0x0F, 0x46, 0x0A},		{cmovna r9, [rdx]}	; r/m64 -> reg64
+
+; implicit evex through ND
+testcase	{0x62, 0xF4, 0x35, 0x10, 0x46, 0x0A},	{cmovbe r25w, cx, [rdx]}	; ndd16 = cond ? r/m16 : reg16
+testcase	{0x62, 0xF4, 0x34, 0x10, 0x46, 0x0A},	{cmovbe r25d, ecx, [rdx]}	; ndd32 = cond ? r/m32 : reg32
+testcase	{0x62, 0xF4, 0xB4, 0x10, 0x46, 0x0A},	{cmovbe r25, rcx, [rdx]}	; ndd64 = cond ? r/m64 : reg64
+testcase	{0x62, 0xF4, 0x35, 0x10, 0x46, 0x0A},	{cmovna r25w, cx, [rdx]}	; ndd16 = cond ? r/m16 : reg16
+testcase	{0x62, 0xF4, 0x34, 0x10, 0x46, 0x0A},	{cmovna r25d, ecx, [rdx]}	; ndd32 = cond ? r/m32 : reg32
+testcase	{0x62, 0xF4, 0xB4, 0x10, 0x46, 0x0A},	{cmovna r25, rcx, [rdx]}	; ndd64 = cond ? r/m64 : reg64
+
+; rex2 variant
+testcase	{0x66, 0xD5, 0xC4, 0x46, 0x0A},		{cmovbe r25w, [rdx]}	; r/m16 -> ereg16
+testcase	{0xD5, 0xC4, 0x46, 0x0A},		{cmovbe r25d, [rdx]}	; r/m32 -> ereg32
+testcase	{0xD5, 0xCC, 0x46, 0x0A},		{cmovbe r25, [rdx]}	; r/m64 -> ereg64
+testcase	{0x66, 0xD5, 0xC4, 0x46, 0x0A},		{cmovna r25w, [rdx]}	; r/m16 -> ereg16
+testcase	{0xD5, 0xC4, 0x46, 0x0A},		{cmovna r25d, [rdx]}	; r/m32 -> ereg32
+testcase	{0xD5, 0xCC, 0x46, 0x0A},		{cmovna r25, [rdx]}	; r/m64 -> ereg64
+
+; - cmovl/cmovnge - cmov if less -
+testcase	{0x66, 0x0F, 0x4C, 0x0A},		{cmovl cx, [rdx]}	; r/m16 -> reg16
+testcase	{0x0F, 0x4C, 0x0A},			{cmovl ecx, [rdx]}	; r/m32 -> reg32
+testcase	{0x4C, 0x0F, 0x4C, 0x0A},		{cmovl r9, [rdx]}	; r/m64 -> reg64
+testcase	{0x66, 0x0F, 0x4C, 0x0A},		{cmovnge cx, [rdx]}	; r/m16 -> reg16
+testcase	{0x0F, 0x4C, 0x0A},			{cmovnge ecx, [rdx]}	; r/m32 -> reg32
+testcase	{0x4C, 0x0F, 0x4C, 0x0A},		{cmovnge r9, [rdx]}	; r/m64 -> reg64
+
+; implicit evex through ND
+testcase	{0x62, 0xF4, 0x35, 0x10, 0x4C, 0x0A},	{cmovl r25w, cx, [rdx]}		; ndd16 = cond ? r/m16 : reg16
+testcase	{0x62, 0xF4, 0x34, 0x10, 0x4C, 0x0A},	{cmovl r25d, ecx, [rdx]}	; ndd32 = cond ? r/m32 : reg32
+testcase	{0x62, 0xF4, 0xB4, 0x10, 0x4C, 0x0A},	{cmovl r25, rcx, [rdx]}		; ndd64 = cond ? r/m64 : reg64
+testcase	{0x62, 0xF4, 0x35, 0x10, 0x4C, 0x0A},	{cmovnge r25w, cx, [rdx]}	; ndd16 = cond ? r/m16 : reg16
+testcase	{0x62, 0xF4, 0x34, 0x10, 0x4C, 0x0A},	{cmovnge r25d, ecx, [rdx]}	; ndd32 = cond ? r/m32 : reg32
+testcase	{0x62, 0xF4, 0xB4, 0x10, 0x4C, 0x0A},	{cmovnge r25, rcx, [rdx]}	; ndd64 = cond ? r/m64 : reg64
+
+; rex2 variant
+testcase	{0x66, 0xD5, 0xC4, 0x4C, 0x0A},		{cmovl r25w, [rdx]}	; r/m16 -> ereg16
+testcase	{0xD5, 0xC4, 0x4C, 0x0A},		{cmovl r25d, [rdx]}	; r/m32 -> ereg32
+testcase	{0xD5, 0xCC, 0x4C, 0x0A},		{cmovl r25, [rdx]}	; r/m64 -> ereg64
+testcase	{0x66, 0xD5, 0xC4, 0x4C, 0x0A},		{cmovnge r25w, [rdx]}	; r/m16 -> ereg16
+testcase	{0xD5, 0xC4, 0x4C, 0x0A},		{cmovnge r25d, [rdx]}	; r/m32 -> ereg32
+testcase	{0xD5, 0xCC, 0x4C, 0x0A},		{cmovnge r25, [rdx]}	; r/m64 -> ereg64
+
+; - cmovle/cmovng - cmov if less or equal -
+testcase	{0x66, 0x0F, 0x4E, 0x0A},		{cmovle cx, [rdx]}	; r/m16 -> reg16
+testcase	{0x0F, 0x4E, 0x0A},			{cmovle ecx, [rdx]}	; r/m32 -> reg32
+testcase	{0x4C, 0x0F, 0x4E, 0x0A},		{cmovle r9, [rdx]}	; r/m64 -> reg64
+testcase	{0x66, 0x0F, 0x4E, 0x0A},		{cmovng cx, [rdx]}	; r/m16 -> reg16
+testcase	{0x0F, 0x4E, 0x0A},			{cmovng ecx, [rdx]}	; r/m32 -> reg32
+testcase	{0x4C, 0x0F, 0x4E, 0x0A},		{cmovng r9, [rdx]}	; r/m64 -> reg64
+
+; implicit evex through ND
+testcase	{0x62, 0xF4, 0x35, 0x10, 0x4E, 0x0A},	{cmovle r25w, cx, [rdx]}	; ndd16 = cond ? r/m16 : reg16
+testcase	{0x62, 0xF4, 0x34, 0x10, 0x4E, 0x0A},	{cmovle r25d, ecx, [rdx]}	; ndd32 = cond ? r/m32 : reg32
+testcase	{0x62, 0xF4, 0xB4, 0x10, 0x4E, 0x0A},	{cmovle r25, rcx, [rdx]}	; ndd64 = cond ? r/m64 : reg64
+testcase	{0x62, 0xF4, 0x35, 0x10, 0x4E, 0x0A},	{cmovng r25w, cx, [rdx]}	; ndd16 = cond ? r/m16 : reg16
+testcase	{0x62, 0xF4, 0x34, 0x10, 0x4E, 0x0A},	{cmovng r25d, ecx, [rdx]}	; ndd32 = cond ? r/m32 : reg32
+testcase	{0x62, 0xF4, 0xB4, 0x10, 0x4E, 0x0A},	{cmovng r25, rcx, [rdx]}	; ndd64 = cond ? r/m64 : reg64
+
+; rex2 variant
+testcase	{0x66, 0xD5, 0xC4, 0x4E, 0x0A},		{cmovle r25w, [rdx]}	; r/m16 -> ereg16
+testcase	{0xD5, 0xC4, 0x4E, 0x0A},		{cmovle r25d, [rdx]}	; r/m32 -> ereg32
+testcase	{0xD5, 0xCC, 0x4E, 0x0A},		{cmovle r25, [rdx]}	; r/m64 -> ereg64
+testcase	{0x66, 0xD5, 0xC4, 0x4E, 0x0A},		{cmovng r25w, [rdx]}	; r/m16 -> ereg16
+testcase	{0xD5, 0xC4, 0x4E, 0x0A},		{cmovng r25d, [rdx]}	; r/m32 -> ereg32
+testcase	{0xD5, 0xCC, 0x4E, 0x0A},		{cmovng r25, [rdx]}	; r/m64 -> ereg64
+
+; - cmovnb/cmovae/cmovnc - cmov if not below -
+testcase	{0x66, 0x0F, 0x43, 0x0A},		{cmovnb cx, [rdx]}	; r/m16 -> reg16
+testcase	{0x0F, 0x43, 0x0A},			{cmovnb ecx, [rdx]}	; r/m32 -> reg32
+testcase	{0x4C, 0x0F, 0x43, 0x0A},		{cmovnb r9, [rdx]}	; r/m64 -> reg64
+testcase	{0x66, 0x0F, 0x43, 0x0A},		{cmovae cx, [rdx]}	; r/m16 -> reg16
+testcase	{0x0F, 0x43, 0x0A},			{cmovae ecx, [rdx]}	; r/m32 -> reg32
+testcase	{0x4C, 0x0F, 0x43, 0x0A},		{cmovae r9, [rdx]}	; r/m64 -> reg64
+
+; implicit evex through ND
+testcase	{0x62, 0xF4, 0x35, 0x10, 0x43, 0x0A},	{cmovnb r25w, cx, [rdx]}	; ndd16 = cond ? r/m16 : reg16
+testcase	{0x62, 0xF4, 0x34, 0x10, 0x43, 0x0A},	{cmovnb r25d, ecx, [rdx]}	; ndd32 = cond ? r/m32 : reg32
+testcase	{0x62, 0xF4, 0xB4, 0x10, 0x43, 0x0A},	{cmovnb r25, rcx, [rdx]}	; ndd64 = cond ? r/m64 : reg64
+testcase	{0x62, 0xF4, 0x35, 0x10, 0x43, 0x0A},	{cmovae r25w, cx, [rdx]}	; ndd16 = cond ? r/m16 : reg16
+testcase	{0x62, 0xF4, 0x34, 0x10, 0x43, 0x0A},	{cmovae r25d, ecx, [rdx]}	; ndd32 = cond ? r/m32 : reg32
+testcase	{0x62, 0xF4, 0xB4, 0x10, 0x43, 0x0A},	{cmovae r25, rcx, [rdx]}	; ndd64 = cond ? r/m64 : reg64
+
+; rex2 variant
+testcase	{0x66, 0xD5, 0xC4, 0x43, 0x0A},		{cmovnb r25w, [rdx]}	; r/m16 -> ereg16
+testcase	{0xD5, 0xC4, 0x43, 0x0A},		{cmovnb r25d, [rdx]}	; r/m32 -> ereg32
+testcase	{0xD5, 0xCC, 0x43, 0x0A},		{cmovnb r25, [rdx]}	; r/m64 -> ereg64
+testcase	{0x66, 0xD5, 0xC4, 0x43, 0x0A},		{cmovae r25w, [rdx]}	; r/m16 -> ereg16
+testcase	{0xD5, 0xC4, 0x43, 0x0A},		{cmovae r25d, [rdx]}	; r/m32 -> ereg32
+testcase	{0xD5, 0xCC, 0x43, 0x0A},		{cmovae r25, [rdx]}	; r/m64 -> ereg64
+
+; - cmovnbe/cmova - cmov if not below or equal -
+testcase	{0x66, 0x0F, 0x47, 0x0A},		{cmovnbe cx, [rdx]}	; r/m16 -> reg16
+testcase	{0x0F, 0x47, 0x0A},			{cmovnbe ecx, [rdx]}	; r/m32 -> reg32
+testcase	{0x4C, 0x0F, 0x47, 0x0A},		{cmovnbe r9, [rdx]}	; r/m64 -> reg64
+testcase	{0x66, 0x0F, 0x47, 0x0A},		{cmova cx, [rdx]}	; r/m16 -> reg16
+testcase	{0x0F, 0x47, 0x0A},			{cmova ecx, [rdx]}	; r/m32 -> reg32
+testcase	{0x4C, 0x0F, 0x47, 0x0A},		{cmova r9, [rdx]}	; r/m64 -> reg64
+
+; implicit evex through ND
+testcase	{0x62, 0xF4, 0x35, 0x10, 0x47, 0x0A},	{cmovnbe r25w, cx, [rdx]}	; ndd16 = cond ? r/m16 : reg16
+testcase	{0x62, 0xF4, 0x34, 0x10, 0x47, 0x0A},	{cmovnbe r25d, ecx, [rdx]}	; ndd32 = cond ? r/m32 : reg32
+testcase	{0x62, 0xF4, 0xB4, 0x10, 0x47, 0x0A},	{cmovnbe r25, rcx, [rdx]}	; ndd64 = cond ? r/m64 : reg64
+testcase	{0x62, 0xF4, 0x35, 0x10, 0x47, 0x0A},	{cmova r25w, cx, [rdx]}		; ndd16 = cond ? r/m16 : reg16
+testcase	{0x62, 0xF4, 0x34, 0x10, 0x47, 0x0A},	{cmova r25d, ecx, [rdx]}	; ndd32 = cond ? r/m32 : reg32
+testcase	{0x62, 0xF4, 0xB4, 0x10, 0x47, 0x0A},	{cmova r25, rcx, [rdx]}		; ndd64 = cond ? r/m64 : reg64
+
+; rex2 variant
+testcase	{0x66, 0xD5, 0xC4, 0x47, 0x0A},		{cmovnbe r25w, [rdx]}	; r/m16 -> ereg16
+testcase	{0xD5, 0xC4, 0x47, 0x0A},		{cmovnbe r25d, [rdx]}	; r/m32 -> ereg32
+testcase	{0xD5, 0xCC, 0x47, 0x0A},		{cmovnbe r25, [rdx]}	; r/m64 -> ereg64
+testcase	{0x66, 0xD5, 0xC4, 0x47, 0x0A},		{cmova r25w, [rdx]}	; r/m16 -> ereg16
+testcase	{0xD5, 0xC4, 0x47, 0x0A},		{cmova r25d, [rdx]}	; r/m32 -> ereg32
+testcase	{0xD5, 0xCC, 0x47, 0x0A},		{cmova r25, [rdx]}	; r/m64 -> ereg64
+
+; - cmovnl/cmovge - cmov if not less -
+testcase	{0x66, 0x0F, 0x4D, 0x0A},		{cmovnl cx, [rdx]}	; r/m16 -> reg16
+testcase	{0x0F, 0x4D, 0x0A},			{cmovnl ecx, [rdx]}	; r/m32 -> reg32
+testcase	{0x4C, 0x0F, 0x4D, 0x0A},		{cmovnl r9, [rdx]}	; r/m64 -> reg64
+testcase	{0x66, 0x0F, 0x4D, 0x0A},		{cmovge cx, [rdx]}	; r/m16 -> reg16
+testcase	{0x0F, 0x4D, 0x0A},			{cmovge ecx, [rdx]}	; r/m32 -> reg32
+testcase	{0x4C, 0x0F, 0x4D, 0x0A},		{cmovge r9, [rdx]}	; r/m64 -> reg64
+
+; implicit evex through ND
+testcase	{0x62, 0xF4, 0x35, 0x10, 0x4D, 0x0A},	{cmovnl r25w, cx, [rdx]}	; ndd16 = cond ? r/m16 : reg16
+testcase	{0x62, 0xF4, 0x34, 0x10, 0x4D, 0x0A},	{cmovnl r25d, ecx, [rdx]}	; ndd32 = cond ? r/m32 : reg32
+testcase	{0x62, 0xF4, 0xB4, 0x10, 0x4D, 0x0A},	{cmovnl r25, rcx, [rdx]}	; ndd64 = cond ? r/m64 : reg64
+testcase	{0x62, 0xF4, 0x35, 0x10, 0x4D, 0x0A},	{cmovge r25w, cx, [rdx]}	; ndd16 = cond ? r/m16 : reg16
+testcase	{0x62, 0xF4, 0x34, 0x10, 0x4D, 0x0A},	{cmovge r25d, ecx, [rdx]}	; ndd32 = cond ? r/m32 : reg32
+testcase	{0x62, 0xF4, 0xB4, 0x10, 0x4D, 0x0A},	{cmovge r25, rcx, [rdx]}	; ndd64 = cond ? r/m64 : reg64
+
+; rex2 variant
+testcase	{0x66, 0xD5, 0xC4, 0x4D, 0x0A},		{cmovnl r25w, [rdx]}	; r/m16 -> ereg16
+testcase	{0xD5, 0xC4, 0x4D, 0x0A},		{cmovnl r25d, [rdx]}	; r/m32 -> ereg32
+testcase	{0xD5, 0xCC, 0x4D, 0x0A},		{cmovnl r25, [rdx]}	; r/m64 -> ereg64
+testcase	{0x66, 0xD5, 0xC4, 0x4D, 0x0A},		{cmovge r25w, [rdx]}	; r/m16 -> ereg16
+testcase	{0xD5, 0xC4, 0x4D, 0x0A},		{cmovge r25d, [rdx]}	; r/m32 -> ereg32
+testcase	{0xD5, 0xCC, 0x4D, 0x0A},		{cmovge r25, [rdx]}	; r/m64 -> ereg64
+
+; - cmovnle/cmovg - cmov if not less or equal -
+testcase	{0x66, 0x0F, 0x4F, 0x0A},		{cmovnle cx, [rdx]}	; r/m16 -> reg16
+testcase	{0x0F, 0x4F, 0x0A},			{cmovnle ecx, [rdx]}	; r/m32 -> reg32
+testcase	{0x4C, 0x0F, 0x4F, 0x0A},		{cmovnle r9, [rdx]}	; r/m64 -> reg64
+testcase	{0x66, 0x0F, 0x4F, 0x0A},		{cmovg cx, [rdx]}	; r/m16 -> reg16
+testcase	{0x0F, 0x4F, 0x0A},			{cmovg ecx, [rdx]}	; r/m32 -> reg32
+testcase	{0x4C, 0x0F, 0x4F, 0x0A},		{cmovg r9, [rdx]}	; r/m64 -> reg64
+
+; implicit evex through ND
+testcase	{0x62, 0xF4, 0x35, 0x10, 0x4F, 0x0A},	{cmovnle r25w, cx, [rdx]}	; ndd16 = cond ? r/m16 : reg16
+testcase	{0x62, 0xF4, 0x34, 0x10, 0x4F, 0x0A},	{cmovnle r25d, ecx, [rdx]}	; ndd32 = cond ? r/m32 : reg32
+testcase	{0x62, 0xF4, 0xB4, 0x10, 0x4F, 0x0A},	{cmovnle r25, rcx, [rdx]}	; ndd64 = cond ? r/m64 : reg64
+testcase	{0x62, 0xF4, 0x35, 0x10, 0x4F, 0x0A},	{cmovg r25w, cx, [rdx]}		; ndd16 = cond ? r/m16 : reg16
+testcase	{0x62, 0xF4, 0x34, 0x10, 0x4F, 0x0A},	{cmovg r25d, ecx, [rdx]}	; ndd32 = cond ? r/m32 : reg32
+testcase	{0x62, 0xF4, 0xB4, 0x10, 0x4F, 0x0A},	{cmovg r25, rcx, [rdx]}		; ndd64 = cond ? r/m64 : reg64
+
+; rex2 variant
+testcase	{0x66, 0xD5, 0xC4, 0x4F, 0x0A},		{cmovnle r25w, [rdx]}	; r/m16 -> ereg16
+testcase	{0xD5, 0xC4, 0x4F, 0x0A},		{cmovnle r25d, [rdx]}	; r/m32 -> ereg32
+testcase	{0xD5, 0xCC, 0x4F, 0x0A},		{cmovnle r25, [rdx]}	; r/m64 -> ereg64
+testcase	{0x66, 0xD5, 0xC4, 0x4F, 0x0A},		{cmovg r25w, [rdx]}	; r/m16 -> ereg16
+testcase	{0xD5, 0xC4, 0x4F, 0x0A},		{cmovg r25d, [rdx]}	; r/m32 -> ereg32
+testcase	{0xD5, 0xCC, 0x4F, 0x0A},		{cmovg r25, [rdx]}	; r/m64 -> ereg64
+
+; - cmovno - cmov if not overflow -
+testcase	{0x66, 0x0F, 0x41, 0x0A},		{cmovno cx, [rdx]}	; r/m16 -> reg16
+testcase	{0x0F, 0x41, 0x0A},			{cmovno ecx, [rdx]}	; r/m32 -> reg32
+testcase	{0x4C, 0x0F, 0x41, 0x0A},		{cmovno r9, [rdx]}	; r/m64 -> reg64
+
+; implicit evex through ND
+testcase	{0x62, 0xF4, 0x35, 0x10, 0x41, 0x0A},	{cmovno r25w, cx, [rdx]}	; ndd16 = cond ? r/m16 : reg16
+testcase	{0x62, 0xF4, 0x34, 0x10, 0x41, 0x0A},	{cmovno r25d, ecx, [rdx]}	; ndd32 = cond ? r/m32 : reg32
+testcase	{0x62, 0xF4, 0xB4, 0x10, 0x41, 0x0A},	{cmovno r25, rcx, [rdx]}	; ndd64 = cond ? r/m64 : reg64
+
+; rex2 variant
+testcase	{0x66, 0xD5, 0xC4, 0x41, 0x0A},		{cmovno r25w, [rdx]}	; r/m16 -> ereg16
+testcase	{0xD5, 0xC4, 0x41, 0x0A},		{cmovno r25d, [rdx]}	; r/m32 -> ereg32
+testcase	{0xD5, 0xCC, 0x41, 0x0A},		{cmovno r25, [rdx]}	; r/m64 -> ereg64
+
+; - cmovnp/cmovpo - cmov if not parity -
+testcase	{0x66, 0x0F, 0x4B, 0x0A},		{cmovnp cx, [rdx]}	; r/m16 -> reg16
+testcase	{0x0F, 0x4B, 0x0A},			{cmovnp ecx, [rdx]}	; r/m32 -> reg32
+testcase	{0x4C, 0x0F, 0x4B, 0x0A},		{cmovnp r9, [rdx]}	; r/m64 -> reg64
+testcase	{0x66, 0x0F, 0x4B, 0x0A},		{cmovpo cx, [rdx]}	; r/m16 -> reg16
+testcase	{0x0F, 0x4B, 0x0A},			{cmovpo ecx, [rdx]}	; r/m32 -> reg32
+testcase	{0x4C, 0x0F, 0x4B, 0x0A},		{cmovpo r9, [rdx]}	; r/m64 -> reg64
+
+; implicit evex through ND
+testcase	{0x62, 0xF4, 0x35, 0x10, 0x4B, 0x0A},	{cmovnp r25w, cx, [rdx]}	; ndd16 = cond ? r/m16 : reg16
+testcase	{0x62, 0xF4, 0x34, 0x10, 0x4B, 0x0A},	{cmovnp r25d, ecx, [rdx]}	; ndd32 = cond ? r/m32 : reg32
+testcase	{0x62, 0xF4, 0xB4, 0x10, 0x4B, 0x0A},	{cmovnp r25, rcx, [rdx]}	; ndd64 = cond ? r/m64 : reg64
+testcase	{0x62, 0xF4, 0x35, 0x10, 0x4B, 0x0A},	{cmovpo r25w, cx, [rdx]}	; ndd16 = cond ? r/m16 : reg16
+testcase	{0x62, 0xF4, 0x34, 0x10, 0x4B, 0x0A},	{cmovpo r25d, ecx, [rdx]}	; ndd32 = cond ? r/m32 : reg32
+testcase	{0x62, 0xF4, 0xB4, 0x10, 0x4B, 0x0A},	{cmovpo r25, rcx, [rdx]}	; ndd64 = cond ? r/m64 : reg64
+
+; rex2 variant
+testcase	{0x66, 0xD5, 0xC4, 0x4B, 0x0A},		{cmovnp r25w, [rdx]}	; r/m16 -> ereg16
+testcase	{0xD5, 0xC4, 0x4B, 0x0A},		{cmovnp r25d, [rdx]}	; r/m32 -> ereg32
+testcase	{0xD5, 0xCC, 0x4B, 0x0A},		{cmovnp r25, [rdx]}	; r/m64 -> ereg64
+testcase	{0x66, 0xD5, 0xC4, 0x4B, 0x0A},		{cmovpo r25w, [rdx]}	; r/m16 -> ereg16
+testcase	{0xD5, 0xC4, 0x4B, 0x0A},		{cmovpo r25d, [rdx]}	; r/m32 -> ereg32
+testcase	{0xD5, 0xCC, 0x4B, 0x0A},		{cmovpo r25, [rdx]}	; r/m64 -> ereg64
+
+; - cmovns - cmov if not signed -
+testcase	{0x66, 0x0F, 0x49, 0x0A},		{cmovns cx, [rdx]}	; r/m16 -> reg16
+testcase	{0x0F, 0x49, 0x0A},			{cmovns ecx, [rdx]}	; r/m32 -> reg32
+testcase	{0x4C, 0x0F, 0x49, 0x0A},		{cmovns r9, [rdx]}	; r/m64 -> reg64
+
+; implicit evex through ND
+testcase	{0x62, 0xF4, 0x35, 0x10, 0x49, 0x0A},	{cmovns r25w, cx, [rdx]}	; ndd16 = cond ? r/m16 : reg16
+testcase	{0x62, 0xF4, 0x34, 0x10, 0x49, 0x0A},	{cmovns r25d, ecx, [rdx]}	; ndd32 = cond ? r/m32 : reg32
+testcase	{0x62, 0xF4, 0xB4, 0x10, 0x49, 0x0A},	{cmovns r25, rcx, [rdx]}	; ndd64 = cond ? r/m64 : reg64
+
+; rex2 variant
+testcase	{0x66, 0xD5, 0xC4, 0x49, 0x0A},		{cmovns r25w, [rdx]}	; r/m16 -> ereg16
+testcase	{0xD5, 0xC4, 0x49, 0x0A},		{cmovns r25d, [rdx]}	; r/m32 -> ereg32
+testcase	{0xD5, 0xCC, 0x49, 0x0A},		{cmovns r25, [rdx]}	; r/m64 -> ereg64
+
+; - cmovnz/cmovne - cmov if not zero -
+testcase	{0x66, 0x0F, 0x45, 0x0A},		{cmovnz cx, [rdx]}	; r/m16 -> reg16
+testcase	{0x0F, 0x45, 0x0A},			{cmovnz ecx, [rdx]}	; r/m32 -> reg32
+testcase	{0x4C, 0x0F, 0x45, 0x0A},		{cmovnz r9, [rdx]}	; r/m64 -> reg64
+testcase	{0x66, 0x0F, 0x45, 0x0A},		{cmovne cx, [rdx]}	; r/m16 -> reg16
+testcase	{0x0F, 0x45, 0x0A},			{cmovne ecx, [rdx]}	; r/m32 -> reg32
+testcase	{0x4C, 0x0F, 0x45, 0x0A},		{cmovne r9, [rdx]}	; r/m64 -> reg64
+
+; implicit evex through ND
+testcase	{0x62, 0xF4, 0x35, 0x10, 0x45, 0x0A},	{cmovnz r25w, cx, [rdx]}	; ndd16 = cond ? r/m16 : reg16
+testcase	{0x62, 0xF4, 0x34, 0x10, 0x45, 0x0A},	{cmovnz r25d, ecx, [rdx]}	; ndd32 = cond ? r/m32 : reg32
+testcase	{0x62, 0xF4, 0xB4, 0x10, 0x45, 0x0A},	{cmovnz r25, rcx, [rdx]}	; ndd64 = cond ? r/m64 : reg64
+testcase	{0x62, 0xF4, 0x35, 0x10, 0x45, 0x0A},	{cmovne r25w, cx, [rdx]}	; ndd16 = cond ? r/m16 : reg16
+testcase	{0x62, 0xF4, 0x34, 0x10, 0x45, 0x0A},	{cmovne r25d, ecx, [rdx]}	; ndd32 = cond ? r/m32 : reg32
+testcase	{0x62, 0xF4, 0xB4, 0x10, 0x45, 0x0A},	{cmovne r25, rcx, [rdx]}	; ndd64 = cond ? r/m64 : reg64
+
+; rex2 variant
+testcase	{0x66, 0xD5, 0xC4, 0x45, 0x0A},		{cmovnz r25w, [rdx]}	; r/m16 -> ereg16
+testcase	{0xD5, 0xC4, 0x45, 0x0A},		{cmovnz r25d, [rdx]}	; r/m32 -> ereg32
+testcase	{0xD5, 0xCC, 0x45, 0x0A},		{cmovnz r25, [rdx]}	; r/m64 -> ereg64
+testcase	{0x66, 0xD5, 0xC4, 0x45, 0x0A},		{cmovne r25w, [rdx]}	; r/m16 -> ereg16
+testcase	{0xD5, 0xC4, 0x45, 0x0A},		{cmovne r25d, [rdx]}	; r/m32 -> ereg32
+testcase	{0xD5, 0xCC, 0x45, 0x0A},		{cmovne r25, [rdx]}	; r/m64 -> ereg64
+
+; - cmovo - cmov if overflow -
+testcase	{0x66, 0x0F, 0x40, 0x0A},		{cmovo cx, [rdx]}	; r/m16 -> reg16
+testcase	{0x0F, 0x40, 0x0A},			{cmovo ecx, [rdx]}	; r/m32 -> reg32
+testcase	{0x4C, 0x0F, 0x40, 0x0A},		{cmovo r9, [rdx]}	; r/m64 -> reg64
+
+; implicit evex through ND
+testcase	{0x62, 0xF4, 0x35, 0x10, 0x40, 0x0A},	{cmovo r25w, cx, [rdx]}		; ndd16 = cond ? r/m16 : reg16
+testcase	{0x62, 0xF4, 0x34, 0x10, 0x40, 0x0A},	{cmovo r25d, ecx, [rdx]}	; ndd32 = cond ? r/m32 : reg32
+testcase	{0x62, 0xF4, 0xB4, 0x10, 0x40, 0x0A},	{cmovo r25, rcx, [rdx]}		; ndd64 = cond ? r/m64 : reg64
+
+; rex2 variant
+testcase	{0x66, 0xD5, 0xC4, 0x40, 0x0A},		{cmovo r25w, [rdx]}	; r/m16 -> ereg16
+testcase	{0xD5, 0xC4, 0x40, 0x0A},		{cmovo r25d, [rdx]}	; r/m32 -> ereg32
+testcase	{0xD5, 0xCC, 0x40, 0x0A},		{cmovo r25, [rdx]}	; r/m64 -> ereg64
+
+; - cmovp/cmovpe - cmov if parity -
+testcase	{0x66, 0x0F, 0x4A, 0x0A},		{cmovp cx, [rdx]}	; r/m16 -> reg16
+testcase	{0x0F, 0x4A, 0x0A},			{cmovp ecx, [rdx]}	; r/m32 -> reg32
+testcase	{0x4C, 0x0F, 0x4A, 0x0A},		{cmovp r9, [rdx]}	; r/m64 -> reg64
+testcase	{0x66, 0x0F, 0x4A, 0x0A},		{cmovpe cx, [rdx]}	; r/m16 -> reg16
+testcase	{0x0F, 0x4A, 0x0A},			{cmovpe ecx, [rdx]}	; r/m32 -> reg32
+testcase	{0x4C, 0x0F, 0x4A, 0x0A},		{cmovpe r9, [rdx]}	; r/m64 -> reg64
+
+; implicit evex through ND
+testcase	{0x62, 0xF4, 0x35, 0x10, 0x4A, 0x0A},	{cmovp r25w, cx, [rdx]}		; ndd16 = cond ? r/m16 : reg16
+testcase	{0x62, 0xF4, 0x34, 0x10, 0x4A, 0x0A},	{cmovp r25d, ecx, [rdx]}	; ndd32 = cond ? r/m32 : reg32
+testcase	{0x62, 0xF4, 0xB4, 0x10, 0x4A, 0x0A},	{cmovp r25, rcx, [rdx]}		; ndd64 = cond ? r/m64 : reg64
+testcase	{0x62, 0xF4, 0x35, 0x10, 0x4A, 0x0A},	{cmovpe r25w, cx, [rdx]}	; ndd16 = cond ? r/m16 : reg16
+testcase	{0x62, 0xF4, 0x34, 0x10, 0x4A, 0x0A},	{cmovpe r25d, ecx, [rdx]}	; ndd32 = cond ? r/m32 : reg32
+testcase	{0x62, 0xF4, 0xB4, 0x10, 0x4A, 0x0A},	{cmovpe r25, rcx, [rdx]}	; ndd64 = cond ? r/m64 : reg64
+
+; rex2 variant
+testcase	{0x66, 0xD5, 0xC4, 0x4A, 0x0A},		{cmovp r25w, [rdx]}	; r/m16 -> ereg16
+testcase	{0xD5, 0xC4, 0x4A, 0x0A},		{cmovp r25d, [rdx]}	; r/m32 -> ereg32
+testcase	{0xD5, 0xCC, 0x4A, 0x0A},		{cmovp r25, [rdx]}	; r/m64 -> ereg64
+testcase	{0x66, 0xD5, 0xC4, 0x4A, 0x0A},		{cmovpe r25w, [rdx]}	; r/m16 -> ereg16
+testcase	{0xD5, 0xC4, 0x4A, 0x0A},		{cmovpe r25d, [rdx]}	; r/m32 -> ereg32
+testcase	{0xD5, 0xCC, 0x4A, 0x0A},		{cmovpe r25, [rdx]}	; r/m64 -> ereg64
+
+; - cmovs - cmov if signed -
+testcase	{0x66, 0x0F, 0x48, 0x0A},		{cmovs cx, [rdx]}	; r/m16 -> reg16
+testcase	{0x0F, 0x48, 0x0A},			{cmovs ecx, [rdx]}	; r/m32 -> reg32
+testcase	{0x4C, 0x0F, 0x48, 0x0A},		{cmovs r9, [rdx]}	; r/m64 -> reg64
+
+; implicit evex through ND
+testcase	{0x62, 0xF4, 0x35, 0x10, 0x48, 0x0A},	{cmovs r25w, cx, [rdx]}		; ndd16 = cond ? r/m16 : reg16
+testcase	{0x62, 0xF4, 0x34, 0x10, 0x48, 0x0A},	{cmovs r25d, ecx, [rdx]}	; ndd32 = cond ? r/m32 : reg32
+testcase	{0x62, 0xF4, 0xB4, 0x10, 0x48, 0x0A},	{cmovs r25, rcx, [rdx]}		; ndd64 = cond ? r/m64 : reg64
+
+; rex2 variant
+testcase	{0x66, 0xD5, 0xC4, 0x48, 0x0A},		{cmovs r25w, [rdx]}	; r/m16 -> ereg16
+testcase	{0xD5, 0xC4, 0x48, 0x0A},		{cmovs r25d, [rdx]}	; r/m32 -> ereg32
+testcase	{0xD5, 0xCC, 0x48, 0x0A},		{cmovs r25, [rdx]}	; r/m64 -> ereg64
+
+; - cmovz/cmove - cmov if zero -
+testcase	{0x66, 0x0F, 0x44, 0x0A},		{cmovz cx, [rdx]}	; r/m16 -> reg16
+testcase	{0x0F, 0x44, 0x0A},			{cmovz ecx, [rdx]}	; r/m32 -> reg32
+testcase	{0x4C, 0x0F, 0x44, 0x0A},		{cmovz r9, [rdx]}	; r/m64 -> reg64
+testcase	{0x66, 0x0F, 0x44, 0x0A},		{cmove cx, [rdx]}	; r/m16 -> reg16
+testcase	{0x0F, 0x44, 0x0A},			{cmove ecx, [rdx]}	; r/m32 -> reg32
+testcase	{0x4C, 0x0F, 0x44, 0x0A},		{cmove r9, [rdx]}	; r/m64 -> reg64
+
+; implicit evex through ND
+testcase	{0x62, 0xF4, 0x35, 0x10, 0x44, 0x0A},	{cmovz r25w, cx, [rdx]}		; ndd16 = cond ? r/m16 : reg16
+testcase	{0x62, 0xF4, 0x34, 0x10, 0x44, 0x0A},	{cmovz r25d, ecx, [rdx]}	; ndd32 = cond ? r/m32 : reg32
+testcase	{0x62, 0xF4, 0xB4, 0x10, 0x44, 0x0A},	{cmovz r25, rcx, [rdx]}		; ndd64 = cond ? r/m64 : reg64
+testcase	{0x62, 0xF4, 0x35, 0x10, 0x44, 0x0A},	{cmove r25w, cx, [rdx]}	; ndd16 = cond ? r/m16 : reg16
+testcase	{0x62, 0xF4, 0x34, 0x10, 0x44, 0x0A},	{cmove r25d, ecx, [rdx]}	; ndd32 = cond ? r/m32 : reg32
+testcase	{0x62, 0xF4, 0xB4, 0x10, 0x44, 0x0A},	{cmove r25, rcx, [rdx]}	; ndd64 = cond ? r/m64 : reg64
+
+; rex2 variant
+testcase	{0x66, 0xD5, 0xC4, 0x44, 0x0A},		{cmovz r25w, [rdx]}	; r/m16 -> ereg16
+testcase	{0xD5, 0xC4, 0x44, 0x0A},		{cmovz r25d, [rdx]}	; r/m32 -> ereg32
+testcase	{0xD5, 0xCC, 0x44, 0x0A},		{cmovz r25, [rdx]}	; r/m64 -> ereg64
+testcase	{0x66, 0xD5, 0xC4, 0x44, 0x0A},		{cmove r25w, [rdx]}	; r/m16 -> ereg16
+testcase	{0xD5, 0xC4, 0x44, 0x0A},		{cmove r25d, [rdx]}	; r/m32 -> ereg32
+testcase	{0xD5, 0xCC, 0x44, 0x0A},		{cmove r25, [rdx]}	; r/m64 -> ereg64
+
+; --- cmpccxadd - conditional add instruction ---
+; - cmpbexadd - add if below or equal -
+testcase	{0xC4, 0x62, 0x71, 0xE6, 0x0A},		{cmpbexadd [rdx], r9d, ecx}	; r/m32 += r32
+testcase	{0xC4, 0x62, 0xF1, 0xE6, 0x0A},		{cmpbexadd [rdx], r9, rcx}	; r/m64 += r64
+testcase	{0x62, 0x4A, 0x75, 0x08, 0xE6, 0x0A},	{cmpbexadd [r26], r25d, ecx}	; r/m32 += r32
+testcase	{0x62, 0x4A, 0xF5, 0x08, 0xE6, 0x0A},	{cmpbexadd [r26], r25, rcx}	; r/m64 += r64
+
+; - cmpbxadd - add if below -
+testcase	{0xC4, 0x62, 0x71, 0xE2, 0x0A},		{cmpbxadd [rdx], r9d, ecx}	; r/m32 += r32
+testcase	{0xC4, 0x62, 0xF1, 0xE2, 0x0A},		{cmpbxadd [rdx], r9, rcx}	; r/m64 += r64
+testcase	{0x62, 0x4A, 0x75, 0x08, 0xE2, 0x0A},	{cmpbxadd [r26], r25d, ecx}	; r/m32 += r32
+testcase	{0x62, 0x4A, 0xF5, 0x08, 0xE2, 0x0A},	{cmpbxadd [r26], r25, rcx}	; r/m64 += r64
+
+; - cmplexadd - add if less or equal -
+testcase	{0xC4, 0x62, 0x71, 0xEE, 0x0A},		{cmplexadd [rdx], r9d, ecx}	; r/m32 += r32
+testcase	{0xC4, 0x62, 0xF1, 0xEE, 0x0A},		{cmplexadd [rdx], r9, rcx}	; r/m64 += r64
+testcase	{0x62, 0x4A, 0x75, 0x08, 0xEE, 0x0A},	{cmplexadd [r26], r25d, ecx}	; r/m32 += r32
+testcase	{0x62, 0x4A, 0xF5, 0x08, 0xEE, 0x0A},	{cmplexadd [r26], r25, rcx}	; r/m64 += r64
+
+; - cmplxadd - add if less or equal -
+testcase	{0xC4, 0x62, 0x71, 0xEC, 0x0A},		{cmplxadd [rdx], r9d, ecx}	; r/m32 += r32
+testcase	{0xC4, 0x62, 0xF1, 0xEC, 0x0A},		{cmplxadd [rdx], r9, rcx}	; r/m64 += r64
+testcase	{0x62, 0x4A, 0x75, 0x08, 0xEC, 0x0A},	{cmplxadd [r26], r25d, ecx}	; r/m32 += r32
+testcase	{0x62, 0x4A, 0xF5, 0x08, 0xEC, 0x0A},	{cmplxadd [r26], r25, rcx}	; r/m64 += r64
+
+; - cmpnbexadd - add if not below or equal -
+testcase	{0xC4, 0x62, 0x71, 0xE7, 0x0A},		{cmpnbexadd [rdx], r9d, ecx}	; r/m32 += r32
+testcase	{0xC4, 0x62, 0xF1, 0xE7, 0x0A},		{cmpnbexadd [rdx], r9, rcx}	; r/m64 += r64
+testcase	{0x62, 0x4A, 0x75, 0x08, 0xE7, 0x0A},	{cmpnbexadd [r26], r25d, ecx}	; r/m32 += r32
+testcase	{0x62, 0x4A, 0xF5, 0x08, 0xE7, 0x0A},	{cmpnbexadd [r26], r25, rcx}	; r/m64 += r64
+
+; - cmpnbxadd - add if not below -
+testcase	{0xC4, 0x62, 0x71, 0xE3, 0x0A},		{cmpnbxadd [rdx], r9d, ecx}	; r/m32 += r32
+testcase	{0xC4, 0x62, 0xF1, 0xE3, 0x0A},		{cmpnbxadd [rdx], r9, rcx}	; r/m64 += r64
+testcase	{0x62, 0x4A, 0x75, 0x08, 0xE3, 0x0A},	{cmpnbxadd [r26], r25d, ecx}	; r/m32 += r32
+testcase	{0x62, 0x4A, 0xF5, 0x08, 0xE3, 0x0A},	{cmpnbxadd [r26], r25, rcx}	; r/m64 += r64
+
+; - cmpnlexadd - add if not less or equal -
+testcase	{0xC4, 0x62, 0x71, 0xEF, 0x0A},		{cmpnlexadd [rdx], r9d, ecx}	; r/m32 += r32
+testcase	{0xC4, 0x62, 0xF1, 0xEF, 0x0A},		{cmpnlexadd [rdx], r9, rcx}	; r/m64 += r64
+testcase	{0x62, 0x4A, 0x75, 0x08, 0xEF, 0x0A},	{cmpnlexadd [r26], r25d, ecx}	; r/m32 += r32
+testcase	{0x62, 0x4A, 0xF5, 0x08, 0xEF, 0x0A},	{cmpnlexadd [r26], r25, rcx}	; r/m64 += r64
+
+; - cmpnlxadd - add if not less -
+testcase	{0xC4, 0x62, 0x71, 0xED, 0x0A},		{cmpnlxadd [rdx], r9d, ecx}	; r/m32 += r32
+testcase	{0xC4, 0x62, 0xF1, 0xED, 0x0A},		{cmpnlxadd [rdx], r9, rcx}	; r/m64 += r64
+testcase	{0x62, 0x4A, 0x75, 0x08, 0xED, 0x0A},	{cmpnlxadd [r26], r25d, ecx}	; r/m32 += r32
+testcase	{0x62, 0x4A, 0xF5, 0x08, 0xED, 0x0A},	{cmpnlxadd [r26], r25, rcx}	; r/m64 += r64
+
+; - cmpnoxadd - add if not overflow -
+testcase	{0xC4, 0x62, 0x71, 0xE1, 0x0A},		{cmpnoxadd [rdx], r9d, ecx}	; r/m32 += r32
+testcase	{0xC4, 0x62, 0xF1, 0xE1, 0x0A},		{cmpnoxadd [rdx], r9, rcx}	; r/m64 += r64
+testcase	{0x62, 0x4A, 0x75, 0x08, 0xE1, 0x0A},	{cmpnoxadd [r26], r25d, ecx}	; r/m32 += r32
+testcase	{0x62, 0x4A, 0xF5, 0x08, 0xE1, 0x0A},	{cmpnoxadd [r26], r25, rcx}	; r/m64 += r64
+
+; - cmpnpxadd - add if not parity -
+testcase	{0xC4, 0x62, 0x71, 0xEB, 0x0A},		{cmpnpxadd [rdx], r9d, ecx}	; r/m32 += r32
+testcase	{0xC4, 0x62, 0xF1, 0xEB, 0x0A},		{cmpnpxadd [rdx], r9, rcx}	; r/m64 += r64
+testcase	{0x62, 0x4A, 0x75, 0x08, 0xEB, 0x0A},	{cmpnpxadd [r26], r25d, ecx}	; r/m32 += r32
+testcase	{0x62, 0x4A, 0xF5, 0x08, 0xEB, 0x0A},	{cmpnpxadd [r26], r25, rcx}	; r/m64 += r64
+
+; - cmpnsxadd - add if not sign -
+testcase	{0xC4, 0x62, 0x71, 0xE9, 0x0A},		{cmpnsxadd [rdx], r9d, ecx}	; r/m32 += r32
+testcase	{0xC4, 0x62, 0xF1, 0xE9, 0x0A},		{cmpnsxadd [rdx], r9, rcx}	; r/m64 += r64
+testcase	{0x62, 0x4A, 0x75, 0x08, 0xE9, 0x0A},	{cmpnsxadd [r26], r25d, ecx}	; r/m32 += r32
+testcase	{0x62, 0x4A, 0xF5, 0x08, 0xE9, 0x0A},	{cmpnsxadd [r26], r25, rcx}	; r/m64 += r64
+
+; - cmpnzxadd - add if not zero -
+testcase	{0xC4, 0x62, 0x71, 0xE5, 0x0A},		{cmpnzxadd [rdx], r9d, ecx}	; r/m32 += r32
+testcase	{0xC4, 0x62, 0xF1, 0xE5, 0x0A},		{cmpnzxadd [rdx], r9, rcx}	; r/m64 += r64
+testcase	{0x62, 0x4A, 0x75, 0x08, 0xE5, 0x0A},	{cmpnzxadd [r26], r25d, ecx}	; r/m32 += r32
+testcase	{0x62, 0x4A, 0xF5, 0x08, 0xE5, 0x0A},	{cmpnzxadd [r26], r25, rcx}	; r/m64 += r64
+
+; - cmpoxadd - add if overflow -
+testcase	{0xC4, 0x62, 0x71, 0xE0, 0x0A},		{cmpoxadd [rdx], r9d, ecx}	; r/m32 += r32
+testcase	{0xC4, 0x62, 0xF1, 0xE0, 0x0A},		{cmpoxadd [rdx], r9, rcx}	; r/m64 += r64
+testcase	{0x62, 0x4A, 0x75, 0x08, 0xE0, 0x0A},	{cmpoxadd [r26], r25d, ecx}	; r/m32 += r32
+testcase	{0x62, 0x4A, 0xF5, 0x08, 0xE0, 0x0A},	{cmpoxadd [r26], r25, rcx}	; r/m64 += r64
+
+; - cmppxadd - add if parity -
+testcase	{0xC4, 0x62, 0x71, 0xEA, 0x0A},		{cmppxadd [rdx], r9d, ecx}	; r/m32 += r32
+testcase	{0xC4, 0x62, 0xF1, 0xEA, 0x0A},		{cmppxadd [rdx], r9, rcx}	; r/m64 += r64
+testcase	{0x62, 0x4A, 0x75, 0x08, 0xEA, 0x0A},	{cmppxadd [r26], r25d, ecx}	; r/m32 += r32
+testcase	{0x62, 0x4A, 0xF5, 0x08, 0xEA, 0x0A},	{cmppxadd [r26], r25, rcx}	; r/m64 += r64
+
+; - cmpsxadd - add if sign -
+testcase	{0xC4, 0x62, 0x71, 0xE8, 0x0A},		{cmpsxadd [rdx], r9d, ecx}	; r/m32 += r32
+testcase	{0xC4, 0x62, 0xF1, 0xE8, 0x0A},		{cmpsxadd [rdx], r9, rcx}	; r/m64 += r64
+testcase	{0x62, 0x4A, 0x75, 0x08, 0xE8, 0x0A},	{cmpsxadd [r26], r25d, ecx}	; r/m32 += r32
+testcase	{0x62, 0x4A, 0xF5, 0x08, 0xE8, 0x0A},	{cmpsxadd [r26], r25, rcx}	; r/m64 += r64
+
+; - cmpzxadd - add if zero -
+testcase	{0xC4, 0x62, 0x71, 0xE4, 0x0A},		{cmpzxadd [rdx], r9d, ecx}	; r/m32 += r32
+testcase	{0xC4, 0x62, 0xF1, 0xE4, 0x0A},		{cmpzxadd [rdx], r9, rcx}	; r/m64 += r64
+testcase	{0x62, 0x4A, 0x75, 0x08, 0xE4, 0x0A},	{cmpzxadd [r26], r25d, ecx}	; r/m32 += r32
+testcase	{0x62, 0x4A, 0xF5, 0x08, 0xE4, 0x0A},	{cmpzxadd [r26], r25, rcx}	; r/m64 += r64
+
diff --git a/travis/test/apx-cond.bin.t b/travis/test/apx-cond.bin.t
new file mode 100644
index 00000000..eb9ef837
--- /dev/null
+++ b/travis/test/apx-cond.bin.t
@@ -0,0 +1,316 @@
+fB
+B
+LB
+fB
+B
+LB
+bô5B
+bô4B
+bô´B
+bô5B
+bô4B
+bô´B
+fÕÄB
+ÕÄB
+ÕÌB
+fÕÄB
+ÕÄB
+ÕÌB
+fF
+F
+LF
+fF
+F
+LF
+bô5F
+bô4F
+bô´F
+bô5F
+bô4F
+bô´F
+fÕÄF
+ÕÄF
+ÕÌF
+fÕÄF
+ÕÄF
+ÕÌF
+fL
+L
+LL
+fL
+L
+LL
+bô5L
+bô4L
+bô´L
+bô5L
+bô4L
+bô´L
+fÕÄL
+ÕÄL
+ÕÌL
+fÕÄL
+ÕÄL
+ÕÌL
+fN
+N
+LN
+fN
+N
+LN
+bô5N
+bô4N
+bô´N
+bô5N
+bô4N
+bô´N
+fÕÄN
+ÕÄN
+ÕÌN
+fÕÄN
+ÕÄN
+ÕÌN
+fC
+C
+LC
+fC
+C
+LC
+bô5C
+bô4C
+bô´C
+bô5C
+bô4C
+bô´C
+fÕÄC
+ÕÄC
+ÕÌC
+fÕÄC
+ÕÄC
+ÕÌC
+fG
+G
+LG
+fG
+G
+LG
+bô5G
+bô4G
+bô´G
+bô5G
+bô4G
+bô´G
+fÕÄG
+ÕÄG
+ÕÌG
+fÕÄG
+ÕÄG
+ÕÌG
+fM
+M
+LM
+fM
+M
+LM
+bô5M
+bô4M
+bô´M
+bô5M
+bô4M
+bô´M
+fÕÄM
+ÕÄM
+ÕÌM
+fÕÄM
+ÕÄM
+ÕÌM
+fO
+O
+LO
+fO
+O
+LO
+bô5O
+bô4O
+bô´O
+bô5O
+bô4O
+bô´O
+fÕÄO
+ÕÄO
+ÕÌO
+fÕÄO
+ÕÄO
+ÕÌO
+fA
+A
+LA
+bô5A
+bô4A
+bô´A
+fÕÄA
+ÕÄA
+ÕÌA
+fK
+K
+LK
+fK
+K
+LK
+bô5K
+bô4K
+bô´K
+bô5K
+bô4K
+bô´K
+fÕÄK
+ÕÄK
+ÕÌK
+fÕÄK
+ÕÄK
+ÕÌK
+fI
+I
+LI
+bô5I
+bô4I
+bô´I
+fÕÄI
+ÕÄI
+ÕÌI
+fE
+E
+LE
+fE
+E
+LE
+bô5E
+bô4E
+bô´E
+bô5E
+bô4E
+bô´E
+fÕÄE
+ÕÄE
+ÕÌE
+fÕÄE
+ÕÄE
+ÕÌE
+f@
+@
+L@
+bô5@
+bô4@
+bô´@
+fÕÄ@
+ÕÄ@
+ÕÌ@
+fJ
+J
+LJ
+fJ
+J
+LJ
+bô5J
+bô4J
+bô´J
+bô5J
+bô4J
+bô´J
+fÕÄJ
+ÕÄJ
+ÕÌJ
+fÕÄJ
+ÕÄJ
+ÕÌJ
+fH
+H
+LH
+bô5H
+bô4H
+bô´H
+fÕÄH
+ÕÄH
+ÕÌH
+fD
+D
+LD
+fD
+D
+LD
+bô5D
+bô4D
+bô´D
+bô5D
+bô4D
+bô´D
+fÕÄD
+ÕÄD
+ÕÌD
+fÕÄD
+ÕÄD
+ÕÌD
+Äbqæ
+Äbñæ
+bJuæ
+bJõæ
+Äbqâ
+Äbñâ
+bJuâ
+bJõâ
+Äbqî
+Äbñî
+bJuî
+bJõî
+Äbqì
+Äbñì
+bJuì
+bJõì
+Äbqç
+Äbñç
+bJuç
+bJõç
+Äbqã
+Äbñã
+bJuã
+bJõã
+Äbqï
+Äbñï
+bJuï
+bJõï
+Äbqí
+Äbñí
+bJuí
+bJõí
+Äbqá
+Äbñá
+bJuá
+bJõá
+Äbqë
+Äbñë
+bJuë
+bJõë
+Äbqé
+Äbñé
+bJué
+bJõé
+Äbqå
+Äbñå
+bJuå
+bJõå
+Äbqà
+Äbñà
+bJuà
+bJõà
+Äbqê
+Äbñê
+bJuê
+bJõê
+Äbqè
+Äbñè
+bJuè
+bJõè
+Äbqä
+Äbñä
+bJuä
+bJõä
diff --git a/travis/test/apx-cond.json b/travis/test/apx-cond.json
new file mode 100644
index 00000000..b47d48cf
--- /dev/null
+++ b/travis/test/apx-cond.json
@@ -0,0 +1,18 @@
+[
+	{
+		"description": "Test apx legacy conditional instruction",
+		"id": "apx-cond",
+		"format": "bin",
+		"source": "apx-cond.asm",
+		"option": "-O0 -DSRC",
+		"target": [
+			{ "output": "apx-cond.bin" }
+		]
+	},
+	{
+		"description": "Test apx legacy conditional instruction",
+		"ref": "apx-cond",
+		"option": "-O0 -DBIN",
+		"update": false
+	}
+]
diff --git a/travis/test/apx.asm b/travis/test/apx.asm
index 70fcc3e6..a80c957f 100644
--- a/travis/test/apx.asm
+++ b/travis/test/apx.asm
@@ -172,452 +172,6 @@ testcase	{0x62, 0x72, 0xF4, 0x0C, 0xF5, 0x0A},	{bzhi{nf} r9, qword [rdx], rcx}
 testcase	{0x62, 0x62, 0x74, 0x08, 0xF5, 0x0A},	{bzhi r25d, dword [rdx], ecx}
 testcase	{0x62, 0x62, 0xF4, 0x08, 0xF5, 0x0A},	{bzhi r25, qword [rdx], rcx}
 
-; --- cmovcc - conditional move instruction ---
-; - cmovb/cmovnae/cmovc - cmov if below -
-testcase	{0x66, 0x0F, 0x42, 0x0A},		{cmovb cx, [rdx]}	; r/m16 -> reg16
-testcase	{0x0F, 0x42, 0x0A},			{cmovb ecx, [rdx]}	; r/m32 -> reg32
-testcase	{0x4C, 0x0F, 0x42, 0x0A},		{cmovb r9, [rdx]}	; r/m64 -> reg64
-testcase	{0x66, 0x0F, 0x42, 0x0A},		{cmovnae cx, [rdx]}	; r/m16 -> reg16
-testcase	{0x0F, 0x42, 0x0A},			{cmovnae ecx, [rdx]}	; r/m32 -> reg32
-testcase	{0x4C, 0x0F, 0x42, 0x0A},		{cmovnae r9, [rdx]}	; r/m64 -> reg64
-
-; implicit evex through ND
-testcase	{0x62, 0xF4, 0x35, 0x10, 0x42, 0x0A},	{cmovb r25w, cx, [rdx]}		; ndd16 = cond ? r/m16 : reg16
-testcase	{0x62, 0xF4, 0x34, 0x10, 0x42, 0x0A},	{cmovb r25d, ecx, [rdx]}	; ndd32 = cond ? r/m32 : reg32
-testcase	{0x62, 0xF4, 0xB4, 0x10, 0x42, 0x0A},	{cmovb r25, rcx, [rdx]}		; ndd64 = cond ? r/m64 : reg64
-testcase	{0x62, 0xF4, 0x35, 0x10, 0x42, 0x0A},	{cmovnae r25w, cx, [rdx]}	; ndd16 = cond ? r/m16 : reg16
-testcase	{0x62, 0xF4, 0x34, 0x10, 0x42, 0x0A},	{cmovnae r25d, ecx, [rdx]}	; ndd32 = cond ? r/m32 : reg32
-testcase	{0x62, 0xF4, 0xB4, 0x10, 0x42, 0x0A},	{cmovnae r25, rcx, [rdx]}	; ndd64 = cond ? r/m64 : reg64
-
-; rex2 variant
-testcase	{0x66, 0xD5, 0xC4, 0x42, 0x0A},		{cmovb r25w, [rdx]}	; r/m16 -> ereg16
-testcase	{0xD5, 0xC4, 0x42, 0x0A},		{cmovb r25d, [rdx]}	; r/m32 -> ereg32
-testcase	{0xD5, 0xCC, 0x42, 0x0A},		{cmovb r25, [rdx]}	; r/m64 -> ereg64
-testcase	{0x66, 0xD5, 0xC4, 0x42, 0x0A},		{cmovnae r25w, [rdx]}	; r/m16 -> ereg16
-testcase	{0xD5, 0xC4, 0x42, 0x0A},		{cmovnae r25d, [rdx]}	; r/m32 -> ereg32
-testcase	{0xD5, 0xCC, 0x42, 0x0A},		{cmovnae r25, [rdx]}	; r/m64 -> ereg64
-
-; - cmovbe/cmovna - cmov if below or equal -
-testcase	{0x66, 0x0F, 0x46, 0x0A},		{cmovbe cx, [rdx]}	; r/m16 -> reg16
-testcase	{0x0F, 0x46, 0x0A},			{cmovbe ecx, [rdx]}	; r/m32 -> reg32
-testcase	{0x4C, 0x0F, 0x46, 0x0A},		{cmovbe r9, [rdx]}	; r/m64 -> reg64
-testcase	{0x66, 0x0F, 0x46, 0x0A},		{cmovna cx, [rdx]}	; r/m16 -> reg16
-testcase	{0x0F, 0x46, 0x0A},			{cmovna ecx, [rdx]}	; r/m32 -> reg32
-testcase	{0x4C, 0x0F, 0x46, 0x0A},		{cmovna r9, [rdx]}	; r/m64 -> reg64
-
-; implicit evex through ND
-testcase	{0x62, 0xF4, 0x35, 0x10, 0x46, 0x0A},	{cmovbe r25w, cx, [rdx]}	; ndd16 = cond ? r/m16 : reg16
-testcase	{0x62, 0xF4, 0x34, 0x10, 0x46, 0x0A},	{cmovbe r25d, ecx, [rdx]}	; ndd32 = cond ? r/m32 : reg32
-testcase	{0x62, 0xF4, 0xB4, 0x10, 0x46, 0x0A},	{cmovbe r25, rcx, [rdx]}	; ndd64 = cond ? r/m64 : reg64
-testcase	{0x62, 0xF4, 0x35, 0x10, 0x46, 0x0A},	{cmovna r25w, cx, [rdx]}	; ndd16 = cond ? r/m16 : reg16
-testcase	{0x62, 0xF4, 0x34, 0x10, 0x46, 0x0A},	{cmovna r25d, ecx, [rdx]}	; ndd32 = cond ? r/m32 : reg32
-testcase	{0x62, 0xF4, 0xB4, 0x10, 0x46, 0x0A},	{cmovna r25, rcx, [rdx]}	; ndd64 = cond ? r/m64 : reg64
-
-; rex2 variant
-testcase	{0x66, 0xD5, 0xC4, 0x46, 0x0A},		{cmovbe r25w, [rdx]}	; r/m16 -> ereg16
-testcase	{0xD5, 0xC4, 0x46, 0x0A},		{cmovbe r25d, [rdx]}	; r/m32 -> ereg32
-testcase	{0xD5, 0xCC, 0x46, 0x0A},		{cmovbe r25, [rdx]}	; r/m64 -> ereg64
-testcase	{0x66, 0xD5, 0xC4, 0x46, 0x0A},		{cmovna r25w, [rdx]}	; r/m16 -> ereg16
-testcase	{0xD5, 0xC4, 0x46, 0x0A},		{cmovna r25d, [rdx]}	; r/m32 -> ereg32
-testcase	{0xD5, 0xCC, 0x46, 0x0A},		{cmovna r25, [rdx]}	; r/m64 -> ereg64
-
-; - cmovl/cmovnge - cmov if less -
-testcase	{0x66, 0x0F, 0x4C, 0x0A},		{cmovl cx, [rdx]}	; r/m16 -> reg16
-testcase	{0x0F, 0x4C, 0x0A},			{cmovl ecx, [rdx]}	; r/m32 -> reg32
-testcase	{0x4C, 0x0F, 0x4C, 0x0A},		{cmovl r9, [rdx]}	; r/m64 -> reg64
-testcase	{0x66, 0x0F, 0x4C, 0x0A},		{cmovnge cx, [rdx]}	; r/m16 -> reg16
-testcase	{0x0F, 0x4C, 0x0A},			{cmovnge ecx, [rdx]}	; r/m32 -> reg32
-testcase	{0x4C, 0x0F, 0x4C, 0x0A},		{cmovnge r9, [rdx]}	; r/m64 -> reg64
-
-; implicit evex through ND
-testcase	{0x62, 0xF4, 0x35, 0x10, 0x4C, 0x0A},	{cmovl r25w, cx, [rdx]}		; ndd16 = cond ? r/m16 : reg16
-testcase	{0x62, 0xF4, 0x34, 0x10, 0x4C, 0x0A},	{cmovl r25d, ecx, [rdx]}	; ndd32 = cond ? r/m32 : reg32
-testcase	{0x62, 0xF4, 0xB4, 0x10, 0x4C, 0x0A},	{cmovl r25, rcx, [rdx]}		; ndd64 = cond ? r/m64 : reg64
-testcase	{0x62, 0xF4, 0x35, 0x10, 0x4C, 0x0A},	{cmovnge r25w, cx, [rdx]}	; ndd16 = cond ? r/m16 : reg16
-testcase	{0x62, 0xF4, 0x34, 0x10, 0x4C, 0x0A},	{cmovnge r25d, ecx, [rdx]}	; ndd32 = cond ? r/m32 : reg32
-testcase	{0x62, 0xF4, 0xB4, 0x10, 0x4C, 0x0A},	{cmovnge r25, rcx, [rdx]}	; ndd64 = cond ? r/m64 : reg64
-
-; rex2 variant
-testcase	{0x66, 0xD5, 0xC4, 0x4C, 0x0A},		{cmovl r25w, [rdx]}	; r/m16 -> ereg16
-testcase	{0xD5, 0xC4, 0x4C, 0x0A},		{cmovl r25d, [rdx]}	; r/m32 -> ereg32
-testcase	{0xD5, 0xCC, 0x4C, 0x0A},		{cmovl r25, [rdx]}	; r/m64 -> ereg64
-testcase	{0x66, 0xD5, 0xC4, 0x4C, 0x0A},		{cmovnge r25w, [rdx]}	; r/m16 -> ereg16
-testcase	{0xD5, 0xC4, 0x4C, 0x0A},		{cmovnge r25d, [rdx]}	; r/m32 -> ereg32
-testcase	{0xD5, 0xCC, 0x4C, 0x0A},		{cmovnge r25, [rdx]}	; r/m64 -> ereg64
-
-; - cmovle/cmovng - cmov if less or equal -
-testcase	{0x66, 0x0F, 0x4E, 0x0A},		{cmovle cx, [rdx]}	; r/m16 -> reg16
-testcase	{0x0F, 0x4E, 0x0A},			{cmovle ecx, [rdx]}	; r/m32 -> reg32
-testcase	{0x4C, 0x0F, 0x4E, 0x0A},		{cmovle r9, [rdx]}	; r/m64 -> reg64
-testcase	{0x66, 0x0F, 0x4E, 0x0A},		{cmovng cx, [rdx]}	; r/m16 -> reg16
-testcase	{0x0F, 0x4E, 0x0A},			{cmovng ecx, [rdx]}	; r/m32 -> reg32
-testcase	{0x4C, 0x0F, 0x4E, 0x0A},		{cmovng r9, [rdx]}	; r/m64 -> reg64
-
-; implicit evex through ND
-testcase	{0x62, 0xF4, 0x35, 0x10, 0x4E, 0x0A},	{cmovle r25w, cx, [rdx]}	; ndd16 = cond ? r/m16 : reg16
-testcase	{0x62, 0xF4, 0x34, 0x10, 0x4E, 0x0A},	{cmovle r25d, ecx, [rdx]}	; ndd32 = cond ? r/m32 : reg32
-testcase	{0x62, 0xF4, 0xB4, 0x10, 0x4E, 0x0A},	{cmovle r25, rcx, [rdx]}	; ndd64 = cond ? r/m64 : reg64
-testcase	{0x62, 0xF4, 0x35, 0x10, 0x4E, 0x0A},	{cmovng r25w, cx, [rdx]}	; ndd16 = cond ? r/m16 : reg16
-testcase	{0x62, 0xF4, 0x34, 0x10, 0x4E, 0x0A},	{cmovng r25d, ecx, [rdx]}	; ndd32 = cond ? r/m32 : reg32
-testcase	{0x62, 0xF4, 0xB4, 0x10, 0x4E, 0x0A},	{cmovng r25, rcx, [rdx]}	; ndd64 = cond ? r/m64 : reg64
-
-; rex2 variant
-testcase	{0x66, 0xD5, 0xC4, 0x4E, 0x0A},		{cmovle r25w, [rdx]}	; r/m16 -> ereg16
-testcase	{0xD5, 0xC4, 0x4E, 0x0A},		{cmovle r25d, [rdx]}	; r/m32 -> ereg32
-testcase	{0xD5, 0xCC, 0x4E, 0x0A},		{cmovle r25, [rdx]}	; r/m64 -> ereg64
-testcase	{0x66, 0xD5, 0xC4, 0x4E, 0x0A},		{cmovng r25w, [rdx]}	; r/m16 -> ereg16
-testcase	{0xD5, 0xC4, 0x4E, 0x0A},		{cmovng r25d, [rdx]}	; r/m32 -> ereg32
-testcase	{0xD5, 0xCC, 0x4E, 0x0A},		{cmovng r25, [rdx]}	; r/m64 -> ereg64
-
-; - cmovnb/cmovae/cmovnc - cmov if not below -
-testcase	{0x66, 0x0F, 0x43, 0x0A},		{cmovnb cx, [rdx]}	; r/m16 -> reg16
-testcase	{0x0F, 0x43, 0x0A},			{cmovnb ecx, [rdx]}	; r/m32 -> reg32
-testcase	{0x4C, 0x0F, 0x43, 0x0A},		{cmovnb r9, [rdx]}	; r/m64 -> reg64
-testcase	{0x66, 0x0F, 0x43, 0x0A},		{cmovae cx, [rdx]}	; r/m16 -> reg16
-testcase	{0x0F, 0x43, 0x0A},			{cmovae ecx, [rdx]}	; r/m32 -> reg32
-testcase	{0x4C, 0x0F, 0x43, 0x0A},		{cmovae r9, [rdx]}	; r/m64 -> reg64
-
-; implicit evex through ND
-testcase	{0x62, 0xF4, 0x35, 0x10, 0x43, 0x0A},	{cmovnb r25w, cx, [rdx]}	; ndd16 = cond ? r/m16 : reg16
-testcase	{0x62, 0xF4, 0x34, 0x10, 0x43, 0x0A},	{cmovnb r25d, ecx, [rdx]}	; ndd32 = cond ? r/m32 : reg32
-testcase	{0x62, 0xF4, 0xB4, 0x10, 0x43, 0x0A},	{cmovnb r25, rcx, [rdx]}	; ndd64 = cond ? r/m64 : reg64
-testcase	{0x62, 0xF4, 0x35, 0x10, 0x43, 0x0A},	{cmovae r25w, cx, [rdx]}	; ndd16 = cond ? r/m16 : reg16
-testcase	{0x62, 0xF4, 0x34, 0x10, 0x43, 0x0A},	{cmovae r25d, ecx, [rdx]}	; ndd32 = cond ? r/m32 : reg32
-testcase	{0x62, 0xF4, 0xB4, 0x10, 0x43, 0x0A},	{cmovae r25, rcx, [rdx]}	; ndd64 = cond ? r/m64 : reg64
-
-; rex2 variant
-testcase	{0x66, 0xD5, 0xC4, 0x43, 0x0A},		{cmovnb r25w, [rdx]}	; r/m16 -> ereg16
-testcase	{0xD5, 0xC4, 0x43, 0x0A},		{cmovnb r25d, [rdx]}	; r/m32 -> ereg32
-testcase	{0xD5, 0xCC, 0x43, 0x0A},		{cmovnb r25, [rdx]}	; r/m64 -> ereg64
-testcase	{0x66, 0xD5, 0xC4, 0x43, 0x0A},		{cmovae r25w, [rdx]}	; r/m16 -> ereg16
-testcase	{0xD5, 0xC4, 0x43, 0x0A},		{cmovae r25d, [rdx]}	; r/m32 -> ereg32
-testcase	{0xD5, 0xCC, 0x43, 0x0A},		{cmovae r25, [rdx]}	; r/m64 -> ereg64
-
-; - cmovnbe/cmova - cmov if not below or equal -
-testcase	{0x66, 0x0F, 0x47, 0x0A},		{cmovnbe cx, [rdx]}	; r/m16 -> reg16
-testcase	{0x0F, 0x47, 0x0A},			{cmovnbe ecx, [rdx]}	; r/m32 -> reg32
-testcase	{0x4C, 0x0F, 0x47, 0x0A},		{cmovnbe r9, [rdx]}	; r/m64 -> reg64
-testcase	{0x66, 0x0F, 0x47, 0x0A},		{cmova cx, [rdx]}	; r/m16 -> reg16
-testcase	{0x0F, 0x47, 0x0A},			{cmova ecx, [rdx]}	; r/m32 -> reg32
-testcase	{0x4C, 0x0F, 0x47, 0x0A},		{cmova r9, [rdx]}	; r/m64 -> reg64
-
-; implicit evex through ND
-testcase	{0x62, 0xF4, 0x35, 0x10, 0x47, 0x0A},	{cmovnbe r25w, cx, [rdx]}	; ndd16 = cond ? r/m16 : reg16
-testcase	{0x62, 0xF4, 0x34, 0x10, 0x47, 0x0A},	{cmovnbe r25d, ecx, [rdx]}	; ndd32 = cond ? r/m32 : reg32
-testcase	{0x62, 0xF4, 0xB4, 0x10, 0x47, 0x0A},	{cmovnbe r25, rcx, [rdx]}	; ndd64 = cond ? r/m64 : reg64
-testcase	{0x62, 0xF4, 0x35, 0x10, 0x47, 0x0A},	{cmova r25w, cx, [rdx]}		; ndd16 = cond ? r/m16 : reg16
-testcase	{0x62, 0xF4, 0x34, 0x10, 0x47, 0x0A},	{cmova r25d, ecx, [rdx]}	; ndd32 = cond ? r/m32 : reg32
-testcase	{0x62, 0xF4, 0xB4, 0x10, 0x47, 0x0A},	{cmova r25, rcx, [rdx]}		; ndd64 = cond ? r/m64 : reg64
-
-; rex2 variant
-testcase	{0x66, 0xD5, 0xC4, 0x47, 0x0A},		{cmovnbe r25w, [rdx]}	; r/m16 -> ereg16
-testcase	{0xD5, 0xC4, 0x47, 0x0A},		{cmovnbe r25d, [rdx]}	; r/m32 -> ereg32
-testcase	{0xD5, 0xCC, 0x47, 0x0A},		{cmovnbe r25, [rdx]}	; r/m64 -> ereg64
-testcase	{0x66, 0xD5, 0xC4, 0x47, 0x0A},		{cmova r25w, [rdx]}	; r/m16 -> ereg16
-testcase	{0xD5, 0xC4, 0x47, 0x0A},		{cmova r25d, [rdx]}	; r/m32 -> ereg32
-testcase	{0xD5, 0xCC, 0x47, 0x0A},		{cmova r25, [rdx]}	; r/m64 -> ereg64
-
-; - cmovnl/cmovge - cmov if not less -
-testcase	{0x66, 0x0F, 0x4D, 0x0A},		{cmovnl cx, [rdx]}	; r/m16 -> reg16
-testcase	{0x0F, 0x4D, 0x0A},			{cmovnl ecx, [rdx]}	; r/m32 -> reg32
-testcase	{0x4C, 0x0F, 0x4D, 0x0A},		{cmovnl r9, [rdx]}	; r/m64 -> reg64
-testcase	{0x66, 0x0F, 0x4D, 0x0A},		{cmovge cx, [rdx]}	; r/m16 -> reg16
-testcase	{0x0F, 0x4D, 0x0A},			{cmovge ecx, [rdx]}	; r/m32 -> reg32
-testcase	{0x4C, 0x0F, 0x4D, 0x0A},		{cmovge r9, [rdx]}	; r/m64 -> reg64
-
-; implicit evex through ND
-testcase	{0x62, 0xF4, 0x35, 0x10, 0x4D, 0x0A},	{cmovnl r25w, cx, [rdx]}	; ndd16 = cond ? r/m16 : reg16
-testcase	{0x62, 0xF4, 0x34, 0x10, 0x4D, 0x0A},	{cmovnl r25d, ecx, [rdx]}	; ndd32 = cond ? r/m32 : reg32
-testcase	{0x62, 0xF4, 0xB4, 0x10, 0x4D, 0x0A},	{cmovnl r25, rcx, [rdx]}	; ndd64 = cond ? r/m64 : reg64
-testcase	{0x62, 0xF4, 0x35, 0x10, 0x4D, 0x0A},	{cmovge r25w, cx, [rdx]}	; ndd16 = cond ? r/m16 : reg16
-testcase	{0x62, 0xF4, 0x34, 0x10, 0x4D, 0x0A},	{cmovge r25d, ecx, [rdx]}	; ndd32 = cond ? r/m32 : reg32
-testcase	{0x62, 0xF4, 0xB4, 0x10, 0x4D, 0x0A},	{cmovge r25, rcx, [rdx]}	; ndd64 = cond ? r/m64 : reg64
-
-; rex2 variant
-testcase	{0x66, 0xD5, 0xC4, 0x4D, 0x0A},		{cmovnl r25w, [rdx]}	; r/m16 -> ereg16
-testcase	{0xD5, 0xC4, 0x4D, 0x0A},		{cmovnl r25d, [rdx]}	; r/m32 -> ereg32
-testcase	{0xD5, 0xCC, 0x4D, 0x0A},		{cmovnl r25, [rdx]}	; r/m64 -> ereg64
-testcase	{0x66, 0xD5, 0xC4, 0x4D, 0x0A},		{cmovge r25w, [rdx]}	; r/m16 -> ereg16
-testcase	{0xD5, 0xC4, 0x4D, 0x0A},		{cmovge r25d, [rdx]}	; r/m32 -> ereg32
-testcase	{0xD5, 0xCC, 0x4D, 0x0A},		{cmovge r25, [rdx]}	; r/m64 -> ereg64
-
-; - cmovnle/cmovg - cmov if not less or equal -
-testcase	{0x66, 0x0F, 0x4F, 0x0A},		{cmovnle cx, [rdx]}	; r/m16 -> reg16
-testcase	{0x0F, 0x4F, 0x0A},			{cmovnle ecx, [rdx]}	; r/m32 -> reg32
-testcase	{0x4C, 0x0F, 0x4F, 0x0A},		{cmovnle r9, [rdx]}	; r/m64 -> reg64
-testcase	{0x66, 0x0F, 0x4F, 0x0A},		{cmovg cx, [rdx]}	; r/m16 -> reg16
-testcase	{0x0F, 0x4F, 0x0A},			{cmovg ecx, [rdx]}	; r/m32 -> reg32
-testcase	{0x4C, 0x0F, 0x4F, 0x0A},		{cmovg r9, [rdx]}	; r/m64 -> reg64
-
-; implicit evex through ND
-testcase	{0x62, 0xF4, 0x35, 0x10, 0x4F, 0x0A},	{cmovnle r25w, cx, [rdx]}	; ndd16 = cond ? r/m16 : reg16
-testcase	{0x62, 0xF4, 0x34, 0x10, 0x4F, 0x0A},	{cmovnle r25d, ecx, [rdx]}	; ndd32 = cond ? r/m32 : reg32
-testcase	{0x62, 0xF4, 0xB4, 0x10, 0x4F, 0x0A},	{cmovnle r25, rcx, [rdx]}	; ndd64 = cond ? r/m64 : reg64
-testcase	{0x62, 0xF4, 0x35, 0x10, 0x4F, 0x0A},	{cmovg r25w, cx, [rdx]}		; ndd16 = cond ? r/m16 : reg16
-testcase	{0x62, 0xF4, 0x34, 0x10, 0x4F, 0x0A},	{cmovg r25d, ecx, [rdx]}	; ndd32 = cond ? r/m32 : reg32
-testcase	{0x62, 0xF4, 0xB4, 0x10, 0x4F, 0x0A},	{cmovg r25, rcx, [rdx]}		; ndd64 = cond ? r/m64 : reg64
-
-; rex2 variant
-testcase	{0x66, 0xD5, 0xC4, 0x4F, 0x0A},		{cmovnle r25w, [rdx]}	; r/m16 -> ereg16
-testcase	{0xD5, 0xC4, 0x4F, 0x0A},		{cmovnle r25d, [rdx]}	; r/m32 -> ereg32
-testcase	{0xD5, 0xCC, 0x4F, 0x0A},		{cmovnle r25, [rdx]}	; r/m64 -> ereg64
-testcase	{0x66, 0xD5, 0xC4, 0x4F, 0x0A},		{cmovg r25w, [rdx]}	; r/m16 -> ereg16
-testcase	{0xD5, 0xC4, 0x4F, 0x0A},		{cmovg r25d, [rdx]}	; r/m32 -> ereg32
-testcase	{0xD5, 0xCC, 0x4F, 0x0A},		{cmovg r25, [rdx]}	; r/m64 -> ereg64
-
-; - cmovno - cmov if not overflow -
-testcase	{0x66, 0x0F, 0x41, 0x0A},		{cmovno cx, [rdx]}	; r/m16 -> reg16
-testcase	{0x0F, 0x41, 0x0A},			{cmovno ecx, [rdx]}	; r/m32 -> reg32
-testcase	{0x4C, 0x0F, 0x41, 0x0A},		{cmovno r9, [rdx]}	; r/m64 -> reg64
-
-; implicit evex through ND
-testcase	{0x62, 0xF4, 0x35, 0x10, 0x41, 0x0A},	{cmovno r25w, cx, [rdx]}	; ndd16 = cond ? r/m16 : reg16
-testcase	{0x62, 0xF4, 0x34, 0x10, 0x41, 0x0A},	{cmovno r25d, ecx, [rdx]}	; ndd32 = cond ? r/m32 : reg32
-testcase	{0x62, 0xF4, 0xB4, 0x10, 0x41, 0x0A},	{cmovno r25, rcx, [rdx]}	; ndd64 = cond ? r/m64 : reg64
-
-; rex2 variant
-testcase	{0x66, 0xD5, 0xC4, 0x41, 0x0A},		{cmovno r25w, [rdx]}	; r/m16 -> ereg16
-testcase	{0xD5, 0xC4, 0x41, 0x0A},		{cmovno r25d, [rdx]}	; r/m32 -> ereg32
-testcase	{0xD5, 0xCC, 0x41, 0x0A},		{cmovno r25, [rdx]}	; r/m64 -> ereg64
-
-; - cmovnp/cmovpo - cmov if not parity -
-testcase	{0x66, 0x0F, 0x4B, 0x0A},		{cmovnp cx, [rdx]}	; r/m16 -> reg16
-testcase	{0x0F, 0x4B, 0x0A},			{cmovnp ecx, [rdx]}	; r/m32 -> reg32
-testcase	{0x4C, 0x0F, 0x4B, 0x0A},		{cmovnp r9, [rdx]}	; r/m64 -> reg64
-testcase	{0x66, 0x0F, 0x4B, 0x0A},		{cmovpo cx, [rdx]}	; r/m16 -> reg16
-testcase	{0x0F, 0x4B, 0x0A},			{cmovpo ecx, [rdx]}	; r/m32 -> reg32
-testcase	{0x4C, 0x0F, 0x4B, 0x0A},		{cmovpo r9, [rdx]}	; r/m64 -> reg64
-
-; implicit evex through ND
-testcase	{0x62, 0xF4, 0x35, 0x10, 0x4B, 0x0A},	{cmovnp r25w, cx, [rdx]}	; ndd16 = cond ? r/m16 : reg16
-testcase	{0x62, 0xF4, 0x34, 0x10, 0x4B, 0x0A},	{cmovnp r25d, ecx, [rdx]}	; ndd32 = cond ? r/m32 : reg32
-testcase	{0x62, 0xF4, 0xB4, 0x10, 0x4B, 0x0A},	{cmovnp r25, rcx, [rdx]}	; ndd64 = cond ? r/m64 : reg64
-testcase	{0x62, 0xF4, 0x35, 0x10, 0x4B, 0x0A},	{cmovpo r25w, cx, [rdx]}	; ndd16 = cond ? r/m16 : reg16
-testcase	{0x62, 0xF4, 0x34, 0x10, 0x4B, 0x0A},	{cmovpo r25d, ecx, [rdx]}	; ndd32 = cond ? r/m32 : reg32
-testcase	{0x62, 0xF4, 0xB4, 0x10, 0x4B, 0x0A},	{cmovpo r25, rcx, [rdx]}	; ndd64 = cond ? r/m64 : reg64
-
-; rex2 variant
-testcase	{0x66, 0xD5, 0xC4, 0x4B, 0x0A},		{cmovnp r25w, [rdx]}	; r/m16 -> ereg16
-testcase	{0xD5, 0xC4, 0x4B, 0x0A},		{cmovnp r25d, [rdx]}	; r/m32 -> ereg32
-testcase	{0xD5, 0xCC, 0x4B, 0x0A},		{cmovnp r25, [rdx]}	; r/m64 -> ereg64
-testcase	{0x66, 0xD5, 0xC4, 0x4B, 0x0A},		{cmovpo r25w, [rdx]}	; r/m16 -> ereg16
-testcase	{0xD5, 0xC4, 0x4B, 0x0A},		{cmovpo r25d, [rdx]}	; r/m32 -> ereg32
-testcase	{0xD5, 0xCC, 0x4B, 0x0A},		{cmovpo r25, [rdx]}	; r/m64 -> ereg64
-
-; - cmovns - cmov if not signed -
-testcase	{0x66, 0x0F, 0x49, 0x0A},		{cmovns cx, [rdx]}	; r/m16 -> reg16
-testcase	{0x0F, 0x49, 0x0A},			{cmovns ecx, [rdx]}	; r/m32 -> reg32
-testcase	{0x4C, 0x0F, 0x49, 0x0A},		{cmovns r9, [rdx]}	; r/m64 -> reg64
-
-; implicit evex through ND
-testcase	{0x62, 0xF4, 0x35, 0x10, 0x49, 0x0A},	{cmovns r25w, cx, [rdx]}	; ndd16 = cond ? r/m16 : reg16
-testcase	{0x62, 0xF4, 0x34, 0x10, 0x49, 0x0A},	{cmovns r25d, ecx, [rdx]}	; ndd32 = cond ? r/m32 : reg32
-testcase	{0x62, 0xF4, 0xB4, 0x10, 0x49, 0x0A},	{cmovns r25, rcx, [rdx]}	; ndd64 = cond ? r/m64 : reg64
-
-; rex2 variant
-testcase	{0x66, 0xD5, 0xC4, 0x49, 0x0A},		{cmovns r25w, [rdx]}	; r/m16 -> ereg16
-testcase	{0xD5, 0xC4, 0x49, 0x0A},		{cmovns r25d, [rdx]}	; r/m32 -> ereg32
-testcase	{0xD5, 0xCC, 0x49, 0x0A},		{cmovns r25, [rdx]}	; r/m64 -> ereg64
-
-; - cmovnz/cmovne - cmov if not zero -
-testcase	{0x66, 0x0F, 0x45, 0x0A},		{cmovnz cx, [rdx]}	; r/m16 -> reg16
-testcase	{0x0F, 0x45, 0x0A},			{cmovnz ecx, [rdx]}	; r/m32 -> reg32
-testcase	{0x4C, 0x0F, 0x45, 0x0A},		{cmovnz r9, [rdx]}	; r/m64 -> reg64
-testcase	{0x66, 0x0F, 0x45, 0x0A},		{cmovne cx, [rdx]}	; r/m16 -> reg16
-testcase	{0x0F, 0x45, 0x0A},			{cmovne ecx, [rdx]}	; r/m32 -> reg32
-testcase	{0x4C, 0x0F, 0x45, 0x0A},		{cmovne r9, [rdx]}	; r/m64 -> reg64
-
-; implicit evex through ND
-testcase	{0x62, 0xF4, 0x35, 0x10, 0x45, 0x0A},	{cmovnz r25w, cx, [rdx]}	; ndd16 = cond ? r/m16 : reg16
-testcase	{0x62, 0xF4, 0x34, 0x10, 0x45, 0x0A},	{cmovnz r25d, ecx, [rdx]}	; ndd32 = cond ? r/m32 : reg32
-testcase	{0x62, 0xF4, 0xB4, 0x10, 0x45, 0x0A},	{cmovnz r25, rcx, [rdx]}	; ndd64 = cond ? r/m64 : reg64
-testcase	{0x62, 0xF4, 0x35, 0x10, 0x45, 0x0A},	{cmovne r25w, cx, [rdx]}	; ndd16 = cond ? r/m16 : reg16
-testcase	{0x62, 0xF4, 0x34, 0x10, 0x45, 0x0A},	{cmovne r25d, ecx, [rdx]}	; ndd32 = cond ? r/m32 : reg32
-testcase	{0x62, 0xF4, 0xB4, 0x10, 0x45, 0x0A},	{cmovne r25, rcx, [rdx]}	; ndd64 = cond ? r/m64 : reg64
-
-; rex2 variant
-testcase	{0x66, 0xD5, 0xC4, 0x45, 0x0A},		{cmovnz r25w, [rdx]}	; r/m16 -> ereg16
-testcase	{0xD5, 0xC4, 0x45, 0x0A},		{cmovnz r25d, [rdx]}	; r/m32 -> ereg32
-testcase	{0xD5, 0xCC, 0x45, 0x0A},		{cmovnz r25, [rdx]}	; r/m64 -> ereg64
-testcase	{0x66, 0xD5, 0xC4, 0x45, 0x0A},		{cmovne r25w, [rdx]}	; r/m16 -> ereg16
-testcase	{0xD5, 0xC4, 0x45, 0x0A},		{cmovne r25d, [rdx]}	; r/m32 -> ereg32
-testcase	{0xD5, 0xCC, 0x45, 0x0A},		{cmovne r25, [rdx]}	; r/m64 -> ereg64
-
-; - cmovo - cmov if overflow -
-testcase	{0x66, 0x0F, 0x40, 0x0A},		{cmovo cx, [rdx]}	; r/m16 -> reg16
-testcase	{0x0F, 0x40, 0x0A},			{cmovo ecx, [rdx]}	; r/m32 -> reg32
-testcase	{0x4C, 0x0F, 0x40, 0x0A},		{cmovo r9, [rdx]}	; r/m64 -> reg64
-
-; implicit evex through ND
-testcase	{0x62, 0xF4, 0x35, 0x10, 0x40, 0x0A},	{cmovo r25w, cx, [rdx]}		; ndd16 = cond ? r/m16 : reg16
-testcase	{0x62, 0xF4, 0x34, 0x10, 0x40, 0x0A},	{cmovo r25d, ecx, [rdx]}	; ndd32 = cond ? r/m32 : reg32
-testcase	{0x62, 0xF4, 0xB4, 0x10, 0x40, 0x0A},	{cmovo r25, rcx, [rdx]}		; ndd64 = cond ? r/m64 : reg64
-
-; rex2 variant
-testcase	{0x66, 0xD5, 0xC4, 0x40, 0x0A},		{cmovo r25w, [rdx]}	; r/m16 -> ereg16
-testcase	{0xD5, 0xC4, 0x40, 0x0A},		{cmovo r25d, [rdx]}	; r/m32 -> ereg32
-testcase	{0xD5, 0xCC, 0x40, 0x0A},		{cmovo r25, [rdx]}	; r/m64 -> ereg64
-
-; - cmovp/cmovpe - cmov if parity -
-testcase	{0x66, 0x0F, 0x4A, 0x0A},		{cmovp cx, [rdx]}	; r/m16 -> reg16
-testcase	{0x0F, 0x4A, 0x0A},			{cmovp ecx, [rdx]}	; r/m32 -> reg32
-testcase	{0x4C, 0x0F, 0x4A, 0x0A},		{cmovp r9, [rdx]}	; r/m64 -> reg64
-testcase	{0x66, 0x0F, 0x4A, 0x0A},		{cmovpe cx, [rdx]}	; r/m16 -> reg16
-testcase	{0x0F, 0x4A, 0x0A},			{cmovpe ecx, [rdx]}	; r/m32 -> reg32
-testcase	{0x4C, 0x0F, 0x4A, 0x0A},		{cmovpe r9, [rdx]}	; r/m64 -> reg64
-
-; implicit evex through ND
-testcase	{0x62, 0xF4, 0x35, 0x10, 0x4A, 0x0A},	{cmovp r25w, cx, [rdx]}		; ndd16 = cond ? r/m16 : reg16
-testcase	{0x62, 0xF4, 0x34, 0x10, 0x4A, 0x0A},	{cmovp r25d, ecx, [rdx]}	; ndd32 = cond ? r/m32 : reg32
-testcase	{0x62, 0xF4, 0xB4, 0x10, 0x4A, 0x0A},	{cmovp r25, rcx, [rdx]}		; ndd64 = cond ? r/m64 : reg64
-testcase	{0x62, 0xF4, 0x35, 0x10, 0x4A, 0x0A},	{cmovpe r25w, cx, [rdx]}	; ndd16 = cond ? r/m16 : reg16
-testcase	{0x62, 0xF4, 0x34, 0x10, 0x4A, 0x0A},	{cmovpe r25d, ecx, [rdx]}	; ndd32 = cond ? r/m32 : reg32
-testcase	{0x62, 0xF4, 0xB4, 0x10, 0x4A, 0x0A},	{cmovpe r25, rcx, [rdx]}	; ndd64 = cond ? r/m64 : reg64
-
-; rex2 variant
-testcase	{0x66, 0xD5, 0xC4, 0x4A, 0x0A},		{cmovp r25w, [rdx]}	; r/m16 -> ereg16
-testcase	{0xD5, 0xC4, 0x4A, 0x0A},		{cmovp r25d, [rdx]}	; r/m32 -> ereg32
-testcase	{0xD5, 0xCC, 0x4A, 0x0A},		{cmovp r25, [rdx]}	; r/m64 -> ereg64
-testcase	{0x66, 0xD5, 0xC4, 0x4A, 0x0A},		{cmovpe r25w, [rdx]}	; r/m16 -> ereg16
-testcase	{0xD5, 0xC4, 0x4A, 0x0A},		{cmovpe r25d, [rdx]}	; r/m32 -> ereg32
-testcase	{0xD5, 0xCC, 0x4A, 0x0A},		{cmovpe r25, [rdx]}	; r/m64 -> ereg64
-
-; - cmovs - cmov if signed -
-testcase	{0x66, 0x0F, 0x48, 0x0A},		{cmovs cx, [rdx]}	; r/m16 -> reg16
-testcase	{0x0F, 0x48, 0x0A},			{cmovs ecx, [rdx]}	; r/m32 -> reg32
-testcase	{0x4C, 0x0F, 0x48, 0x0A},		{cmovs r9, [rdx]}	; r/m64 -> reg64
-
-; implicit evex through ND
-testcase	{0x62, 0xF4, 0x35, 0x10, 0x48, 0x0A},	{cmovs r25w, cx, [rdx]}		; ndd16 = cond ? r/m16 : reg16
-testcase	{0x62, 0xF4, 0x34, 0x10, 0x48, 0x0A},	{cmovs r25d, ecx, [rdx]}	; ndd32 = cond ? r/m32 : reg32
-testcase	{0x62, 0xF4, 0xB4, 0x10, 0x48, 0x0A},	{cmovs r25, rcx, [rdx]}		; ndd64 = cond ? r/m64 : reg64
-
-; rex2 variant
-testcase	{0x66, 0xD5, 0xC4, 0x48, 0x0A},		{cmovs r25w, [rdx]}	; r/m16 -> ereg16
-testcase	{0xD5, 0xC4, 0x48, 0x0A},		{cmovs r25d, [rdx]}	; r/m32 -> ereg32
-testcase	{0xD5, 0xCC, 0x48, 0x0A},		{cmovs r25, [rdx]}	; r/m64 -> ereg64
-
-; - cmovz/cmove - cmov if zero -
-testcase	{0x66, 0x0F, 0x44, 0x0A},		{cmovz cx, [rdx]}	; r/m16 -> reg16
-testcase	{0x0F, 0x44, 0x0A},			{cmovz ecx, [rdx]}	; r/m32 -> reg32
-testcase	{0x4C, 0x0F, 0x44, 0x0A},		{cmovz r9, [rdx]}	; r/m64 -> reg64
-testcase	{0x66, 0x0F, 0x44, 0x0A},		{cmove cx, [rdx]}	; r/m16 -> reg16
-testcase	{0x0F, 0x44, 0x0A},			{cmove ecx, [rdx]}	; r/m32 -> reg32
-testcase	{0x4C, 0x0F, 0x44, 0x0A},		{cmove r9, [rdx]}	; r/m64 -> reg64
-
-; implicit evex through ND
-testcase	{0x62, 0xF4, 0x35, 0x10, 0x44, 0x0A},	{cmovz r25w, cx, [rdx]}		; ndd16 = cond ? r/m16 : reg16
-testcase	{0x62, 0xF4, 0x34, 0x10, 0x44, 0x0A},	{cmovz r25d, ecx, [rdx]}	; ndd32 = cond ? r/m32 : reg32
-testcase	{0x62, 0xF4, 0xB4, 0x10, 0x44, 0x0A},	{cmovz r25, rcx, [rdx]}		; ndd64 = cond ? r/m64 : reg64
-testcase	{0x62, 0xF4, 0x35, 0x10, 0x44, 0x0A},	{cmove r25w, cx, [rdx]}	; ndd16 = cond ? r/m16 : reg16
-testcase	{0x62, 0xF4, 0x34, 0x10, 0x44, 0x0A},	{cmove r25d, ecx, [rdx]}	; ndd32 = cond ? r/m32 : reg32
-testcase	{0x62, 0xF4, 0xB4, 0x10, 0x44, 0x0A},	{cmove r25, rcx, [rdx]}	; ndd64 = cond ? r/m64 : reg64
-
-; rex2 variant
-testcase	{0x66, 0xD5, 0xC4, 0x44, 0x0A},		{cmovz r25w, [rdx]}	; r/m16 -> ereg16
-testcase	{0xD5, 0xC4, 0x44, 0x0A},		{cmovz r25d, [rdx]}	; r/m32 -> ereg32
-testcase	{0xD5, 0xCC, 0x44, 0x0A},		{cmovz r25, [rdx]}	; r/m64 -> ereg64
-testcase	{0x66, 0xD5, 0xC4, 0x44, 0x0A},		{cmove r25w, [rdx]}	; r/m16 -> ereg16
-testcase	{0xD5, 0xC4, 0x44, 0x0A},		{cmove r25d, [rdx]}	; r/m32 -> ereg32
-testcase	{0xD5, 0xCC, 0x44, 0x0A},		{cmove r25, [rdx]}	; r/m64 -> ereg64
-
-; --- cmpccxadd - conditional add instruction ---
-; - cmpbexadd - add if below or equal -
-testcase	{0xC4, 0x62, 0x71, 0xE6, 0x0A},		{cmpbexadd [rdx], r9d, ecx}	; r/m32 += r32
-testcase	{0xC4, 0x62, 0xF1, 0xE6, 0x0A},		{cmpbexadd [rdx], r9, rcx}	; r/m64 += r64
-testcase	{0x62, 0x4A, 0x75, 0x08, 0xE6, 0x0A},	{cmpbexadd [r26], r25d, ecx}	; r/m32 += r32
-testcase	{0x62, 0x4A, 0xF5, 0x08, 0xE6, 0x0A},	{cmpbexadd [r26], r25, rcx}	; r/m64 += r64
-
-; - cmpbxadd - add if below -
-testcase	{0xC4, 0x62, 0x71, 0xE2, 0x0A},		{cmpbxadd [rdx], r9d, ecx}	; r/m32 += r32
-testcase	{0xC4, 0x62, 0xF1, 0xE2, 0x0A},		{cmpbxadd [rdx], r9, rcx}	; r/m64 += r64
-testcase	{0x62, 0x4A, 0x75, 0x08, 0xE2, 0x0A},	{cmpbxadd [r26], r25d, ecx}	; r/m32 += r32
-testcase	{0x62, 0x4A, 0xF5, 0x08, 0xE2, 0x0A},	{cmpbxadd [r26], r25, rcx}	; r/m64 += r64
-
-; - cmplexadd - add if less or equal -
-testcase	{0xC4, 0x62, 0x71, 0xEE, 0x0A},		{cmplexadd [rdx], r9d, ecx}	; r/m32 += r32
-testcase	{0xC4, 0x62, 0xF1, 0xEE, 0x0A},		{cmplexadd [rdx], r9, rcx}	; r/m64 += r64
-testcase	{0x62, 0x4A, 0x75, 0x08, 0xEE, 0x0A},	{cmplexadd [r26], r25d, ecx}	; r/m32 += r32
-testcase	{0x62, 0x4A, 0xF5, 0x08, 0xEE, 0x0A},	{cmplexadd [r26], r25, rcx}	; r/m64 += r64
-
-; - cmplxadd - add if less or equal -
-testcase	{0xC4, 0x62, 0x71, 0xEC, 0x0A},		{cmplxadd [rdx], r9d, ecx}	; r/m32 += r32
-testcase	{0xC4, 0x62, 0xF1, 0xEC, 0x0A},		{cmplxadd [rdx], r9, rcx}	; r/m64 += r64
-testcase	{0x62, 0x4A, 0x75, 0x08, 0xEC, 0x0A},	{cmplxadd [r26], r25d, ecx}	; r/m32 += r32
-testcase	{0x62, 0x4A, 0xF5, 0x08, 0xEC, 0x0A},	{cmplxadd [r26], r25, rcx}	; r/m64 += r64
-
-; - cmpnbexadd - add if not below or equal -
-testcase	{0xC4, 0x62, 0x71, 0xE7, 0x0A},		{cmpnbexadd [rdx], r9d, ecx}	; r/m32 += r32
-testcase	{0xC4, 0x62, 0xF1, 0xE7, 0x0A},		{cmpnbexadd [rdx], r9, rcx}	; r/m64 += r64
-testcase	{0x62, 0x4A, 0x75, 0x08, 0xE7, 0x0A},	{cmpnbexadd [r26], r25d, ecx}	; r/m32 += r32
-testcase	{0x62, 0x4A, 0xF5, 0x08, 0xE7, 0x0A},	{cmpnbexadd [r26], r25, rcx}	; r/m64 += r64
-
-; - cmpnbxadd - add if not below -
-testcase	{0xC4, 0x62, 0x71, 0xE3, 0x0A},		{cmpnbxadd [rdx], r9d, ecx}	; r/m32 += r32
-testcase	{0xC4, 0x62, 0xF1, 0xE3, 0x0A},		{cmpnbxadd [rdx], r9, rcx}	; r/m64 += r64
-testcase	{0x62, 0x4A, 0x75, 0x08, 0xE3, 0x0A},	{cmpnbxadd [r26], r25d, ecx}	; r/m32 += r32
-testcase	{0x62, 0x4A, 0xF5, 0x08, 0xE3, 0x0A},	{cmpnbxadd [r26], r25, rcx}	; r/m64 += r64
-
-; - cmpnlexadd - add if not less or equal -
-testcase	{0xC4, 0x62, 0x71, 0xEF, 0x0A},		{cmpnlexadd [rdx], r9d, ecx}	; r/m32 += r32
-testcase	{0xC4, 0x62, 0xF1, 0xEF, 0x0A},		{cmpnlexadd [rdx], r9, rcx}	; r/m64 += r64
-testcase	{0x62, 0x4A, 0x75, 0x08, 0xEF, 0x0A},	{cmpnlexadd [r26], r25d, ecx}	; r/m32 += r32
-testcase	{0x62, 0x4A, 0xF5, 0x08, 0xEF, 0x0A},	{cmpnlexadd [r26], r25, rcx}	; r/m64 += r64
-
-; - cmpnlxadd - add if not less -
-testcase	{0xC4, 0x62, 0x71, 0xED, 0x0A},		{cmpnlxadd [rdx], r9d, ecx}	; r/m32 += r32
-testcase	{0xC4, 0x62, 0xF1, 0xED, 0x0A},		{cmpnlxadd [rdx], r9, rcx}	; r/m64 += r64
-testcase	{0x62, 0x4A, 0x75, 0x08, 0xED, 0x0A},	{cmpnlxadd [r26], r25d, ecx}	; r/m32 += r32
-testcase	{0x62, 0x4A, 0xF5, 0x08, 0xED, 0x0A},	{cmpnlxadd [r26], r25, rcx}	; r/m64 += r64
-
-; - cmpnoxadd - add if not overflow -
-testcase	{0xC4, 0x62, 0x71, 0xE1, 0x0A},		{cmpnoxadd [rdx], r9d, ecx}	; r/m32 += r32
-testcase	{0xC4, 0x62, 0xF1, 0xE1, 0x0A},		{cmpnoxadd [rdx], r9, rcx}	; r/m64 += r64
-testcase	{0x62, 0x4A, 0x75, 0x08, 0xE1, 0x0A},	{cmpnoxadd [r26], r25d, ecx}	; r/m32 += r32
-testcase	{0x62, 0x4A, 0xF5, 0x08, 0xE1, 0x0A},	{cmpnoxadd [r26], r25, rcx}	; r/m64 += r64
-
-; - cmpnpxadd - add if not parity -
-testcase	{0xC4, 0x62, 0x71, 0xEB, 0x0A},		{cmpnpxadd [rdx], r9d, ecx}	; r/m32 += r32
-testcase	{0xC4, 0x62, 0xF1, 0xEB, 0x0A},		{cmpnpxadd [rdx], r9, rcx}	; r/m64 += r64
-testcase	{0x62, 0x4A, 0x75, 0x08, 0xEB, 0x0A},	{cmpnpxadd [r26], r25d, ecx}	; r/m32 += r32
-testcase	{0x62, 0x4A, 0xF5, 0x08, 0xEB, 0x0A},	{cmpnpxadd [r26], r25, rcx}	; r/m64 += r64
-
-; - cmpnsxadd - add if not sign -
-testcase	{0xC4, 0x62, 0x71, 0xE9, 0x0A},		{cmpnsxadd [rdx], r9d, ecx}	; r/m32 += r32
-testcase	{0xC4, 0x62, 0xF1, 0xE9, 0x0A},		{cmpnsxadd [rdx], r9, rcx}	; r/m64 += r64
-testcase	{0x62, 0x4A, 0x75, 0x08, 0xE9, 0x0A},	{cmpnsxadd [r26], r25d, ecx}	; r/m32 += r32
-testcase	{0x62, 0x4A, 0xF5, 0x08, 0xE9, 0x0A},	{cmpnsxadd [r26], r25, rcx}	; r/m64 += r64
-
-; - cmpnzxadd - add if not zero -
-testcase	{0xC4, 0x62, 0x71, 0xE5, 0x0A},		{cmpnzxadd [rdx], r9d, ecx}	; r/m32 += r32
-testcase	{0xC4, 0x62, 0xF1, 0xE5, 0x0A},		{cmpnzxadd [rdx], r9, rcx}	; r/m64 += r64
-testcase	{0x62, 0x4A, 0x75, 0x08, 0xE5, 0x0A},	{cmpnzxadd [r26], r25d, ecx}	; r/m32 += r32
-testcase	{0x62, 0x4A, 0xF5, 0x08, 0xE5, 0x0A},	{cmpnzxadd [r26], r25, rcx}	; r/m64 += r64
-
-; - cmpoxadd - add if overflow -
-testcase	{0xC4, 0x62, 0x71, 0xE0, 0x0A},		{cmpoxadd [rdx], r9d, ecx}	; r/m32 += r32
-testcase	{0xC4, 0x62, 0xF1, 0xE0, 0x0A},		{cmpoxadd [rdx], r9, rcx}	; r/m64 += r64
-testcase	{0x62, 0x4A, 0x75, 0x08, 0xE0, 0x0A},	{cmpoxadd [r26], r25d, ecx}	; r/m32 += r32
-testcase	{0x62, 0x4A, 0xF5, 0x08, 0xE0, 0x0A},	{cmpoxadd [r26], r25, rcx}	; r/m64 += r64
-
-; - cmppxadd - add if parity -
-testcase	{0xC4, 0x62, 0x71, 0xEA, 0x0A},		{cmppxadd [rdx], r9d, ecx}	; r/m32 += r32
-testcase	{0xC4, 0x62, 0xF1, 0xEA, 0x0A},		{cmppxadd [rdx], r9, rcx}	; r/m64 += r64
-testcase	{0x62, 0x4A, 0x75, 0x08, 0xEA, 0x0A},	{cmppxadd [r26], r25d, ecx}	; r/m32 += r32
-testcase	{0x62, 0x4A, 0xF5, 0x08, 0xEA, 0x0A},	{cmppxadd [r26], r25, rcx}	; r/m64 += r64
-
-; - cmpsxadd - add if sign -
-testcase	{0xC4, 0x62, 0x71, 0xE8, 0x0A},		{cmpsxadd [rdx], r9d, ecx}	; r/m32 += r32
-testcase	{0xC4, 0x62, 0xF1, 0xE8, 0x0A},		{cmpsxadd [rdx], r9, rcx}	; r/m64 += r64
-testcase	{0x62, 0x4A, 0x75, 0x08, 0xE8, 0x0A},	{cmpsxadd [r26], r25d, ecx}	; r/m32 += r32
-testcase	{0x62, 0x4A, 0xF5, 0x08, 0xE8, 0x0A},	{cmpsxadd [r26], r25, rcx}	; r/m64 += r64
-
-; - cmpzxadd - add if zero -
-testcase	{0xC4, 0x62, 0x71, 0xE4, 0x0A},		{cmpzxadd [rdx], r9d, ecx}	; r/m32 += r32
-testcase	{0xC4, 0x62, 0xF1, 0xE4, 0x0A},		{cmpzxadd [rdx], r9, rcx}	; r/m64 += r64
-testcase	{0x62, 0x4A, 0x75, 0x08, 0xE4, 0x0A},	{cmpzxadd [r26], r25d, ecx}	; r/m32 += r32
-testcase	{0x62, 0x4A, 0xF5, 0x08, 0xE4, 0x0A},	{cmpzxadd [r26], r25, rcx}	; r/m64 += r64
-
 ; --- crc32 instruction ---
 ; legacy crc32
 testcase	{0xF2, 0x0F, 0x38, 0xF0, 0x0A},		{crc32 ecx, byte [rdx]}		; reg32 += crc32(r/m8)
diff --git a/travis/test/apx.bin.t b/travis/test/apx.bin.t
index 5eb6cac11d0d436a77e5df696335ed7893dc619b..2b512635331957060a9ce07e5b779a300528fff2 100644
GIT binary patch
delta 12
UcmbO)y_|o;2gc1W*tfF+03>q-Z~y=R

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